CY8C9520A_10 CYPRESS [Cypress Semiconductor], CY8C9520A_10 Datasheet - Page 11

• Manufacturer Part Number: CY8C9520A_10
• Description: 20, 40, and 60 Bit I/O Expander with EEPROM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Register Mapping Table
The register address is auto-incrementing. If the master device
writes or reads data to or from one register and then continues
data transfer in the same I
written or read to or from the following registers. For example, if
the first byte is sent to the Output Port 1 register, then the next
bytes are written to Output Port 2, Output Port 3, Output Port 4
etc. The first byte of each write transaction is treated as the
register address.
To read data from a seires of registers, the master device must
write the starting register address byte then perform a start and
series of read transactions. If no address was sent, reads start
from address 0.
To read a specific register address, the master device must write
the register address byte, then perform a start and read trans-
action.
See
The device’s register mapping is listed in
Table 7. The Device Register Address Map
Document Number: 38-12036 Rev. *E
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
Address
Figure 7
on page 10.
Input Port 0
Input Port 1
Input Port 2
Input Port 3
Input Port 4
Input Port 5
Input Port 6
Input Port 7
Output Port 0
Output Port 1
Output Port 2
Output Port 3
Output Port 4
Output Port 5
Output Port 6
Output Port 7
Interrupt Status Port 0
Interrupt Status Port 1
Interrupt Status Port 2
Interrupt Status Port 3
Interrupt Status Port 4
Interrupt Status Port 5
Interrupt Status Port 6
Interrupt Status Port 7
Port Select
Interrupt Mask
Register
2
C transaction, sequential bytes are
Table
None
None
None
None
None
None
None
None
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
Register Value
7.
Default
Table 7. The Device Register Address Map (continued)
Register Descriptions
The registers for the CY8C95xx are described in the sections
that follow. Note that the PWM registers are located at addresses
28h to 2Bh.
Input Port Registers (00h - 07h)
These registers represent actual logical levels on the pins and
are used for I/O port reading operations. They are read only. The
Inversion registers changes the state of reads to these ports.
Output Port Registers (08h - 0Fh)
These registers are used for writing data to GPIO ports. By
default, all ports are in the pull up mode allowing quasi-bidirec-
tional I/O. To allow input operations without reconfiguration,
these registers have to store ’1’s.
Output register data also affects pin states when PWMs are
enabled. See
See
The Inversion registers have no effect on these ports.
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
Address
Figure 7
on page 10 illustrates port read/write procedures.
Table 8
Select PWM for Port Output 00h
Inversion
Pin Direction - Input/Output
Drive Mode - Pull Up
Drive Mode - Pull Down
Drive Mode - Open Drain
High
Drive Mode - Open Drain
Low
Drive Mode - Strong
Drive Mode - Slow Strong
Drive Mode - High-Z
Reserved
Reserved
Reserved
Reserved
PWM Select
Config PWM
Period PWM
Pulse Width PWM
Programmable Divider
Enable WDE, EEE, EERO
Device ID/Status
Watchdog
Command
CY8C9540A, CY8C9560A
on page 12 for details.
Register
CY8C9520A
00h
00h
FFh
00h
00h
00h
00h
00h
00h
None
None
None
None
00h
00h
FFh
80h
FFh
00h
00h
00h
20h/40h/60h
Register Value
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