KSZ8041NLJ_10 MICREL [Micrel Semiconductor], KSZ8041NLJ_10 Datasheet - Page 14

• Manufacturer Part Number: KSZ8041NLJ_10
• Description: 10/100 Ethernet Transceiver with Extended Temperature Support
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
MII Management (MIIM) Interface
The KSZ8041NLJ supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041NLJ.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Additional
details on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:
The KSZ8041NLJ supports MIIM in both MII mode and RMII mode.
The following table shows the MII Management frame format for the KSZ8041NLJ.
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ8041NLJ PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable
and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are
used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
By default, the KSZ8041NLJ is configured in MII mode after it is power-up or reset with the following:
April 2010
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•
•
•
•
•
•
•
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Read
Write
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ8041NLJ devices. Each KSZ8041NLJ device is assigned a PHY address
between 1 and 7 by the PHYAD[2:0] strapping pins.
An internal addressable set of thirteen 16-bit MDIO registers. Register [0:6] are required, and their functions are
defined by the IEEE 802.3u Specification. The additional registers are provided for expanded functionality.
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting).
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Read/Write
OP Code
10
01
Table 1. MII Management Frame Format
PHY
Address
Bits [4:0]
00AAA
00AAA
14
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
Data
Bits [15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
M9999-040110-1.0
KSZ8041NLJ
Idle
Z
Z