CY8C20110_09 CYPRESS [Cypress Semiconductor], CY8C20110_09 Datasheet - Page 7

• Manufacturer Part Number: CY8C20110_09
• Description: CapSense Express Button Capacitive Controllers
• Manufacturer: CYPRESS [Cypress Semiconductor]

I
The CapSense Express devices support the industry standard I
■
■
■
■
The I
I
The device uses a seven bit addressing protocol. The I
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I
Table 4. I
I
‘Clock stretching’ or ‘bus stalling’ in I
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I
device, the CapSense Express stalls the I
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I
with the CapSense Express device.
Document Number: 001-54606 Rev. **
2
2
2
C Clock Stretching
Configuring the device
Reading the status and data registers of the device
Controlling device operation
Executing commands
C Interface
C Device Addressing
7 Bit Slave
Address
2
C address can be modified during configuration.
75
75
1
1
2
2
C Address Examples
C master communicates with the CapSense Express
D7
0
0
1
1
2
C compliant master to communicate
D6
0
0
0
0
2
D5
C communication protocol
0
0
0
0
D4
2
0
0
1
1
C bus after the
D3
0
0
0
0
2
C data transfer is always initiated by the master sending a one byte address:
D2
0
0
1
1
2
C protocol, which can be used for:
If the I
software I
of time (as specified in
page 8) for each register write and read operation before the next
bit is transmitted. The I
should be high) before the I
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
“Format for Register Write and Read”
read.
D1
1
1
1
1
CY8C20110/CY8C20180/CY8C20160
2
C master does not support clock stretching (a bit banged
0(W)
0(W)
1(W)
1(R)
2
D0
C Master), the master must wait for a specific amount
“Format for Register Write and Read”
2
CY8C20140/CY8C20142
C master must check the SCL status (it
2
8 Bit Slave Address
C master initiates any data transfer
02
03
96
97
on page 8 for write and
2
C addresses.
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