CY8C20110_09 CYPRESS [Cypress Semiconductor], CY8C20110_09 Datasheet
CY8C20110_09
Related parts for CY8C20110_09
CY8C20110_09 Summary of contents
Page 1
Features 10/8/6/4 Capacitive Button Input ■ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, ❐ and sizes Target Applications ...
Page 2
Pinouts Figure 1. Pin Diagram - 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) Table 1. Pin Definitions – 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons) Pin No. Pin Name 1 GP0[0] 2 GP0[1] 2 ...
Page 3
Figure 2. Pin Diagram – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) Table 2. Pin Definitions – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons) Pin No Name 1 GP0[3] 2 CSint 3 GP0[4] 4 ...
Page 4
Figure 3. Pin Diagram - 8-Pin SOIC- CY8C20142 (4 Button) Table 3. Pin Definitions - 8-Pin SOIC - CY8C20142 (4 Button) Pin GP1[0] 5 GP1[1] 6 GP0[0] 7 GP0[1] 8 ...
Page 5
Typical Circuits Circuit-1: Five Button and Five LED with I Circuit 2 - Two Buttons and Two LEDs with I Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 2 C Interface 2 C Interface CY8C20140/CY8C20142 Page [+] ...
Page 6
Circuit 3 - Compatibility with 1.8V I Note 1.8V ≤ VDD_I2C ≤ VDD_CE and 2.4V ≤ VDD_CE ≤ 5.25V Circuit 4 - Powering Down CapSense Express Device for Low Power Requirements Output enable LDO Master Or Host For low ...
Page 7
I C Interface The CapSense Express devices support the industry standard I Configuring the device ■ Reading the status and data registers of the device ■ Controlling device operation ■ Executing commands ■ 2 The I C address can ...
Page 8
Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr Register read format Start Slave Addr + W A Reg Addr Start Slave Addr + R A Data Legends: Master A - ACK ...
Page 9
Operating Modes Commands Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowl- edgment times in normal mode, ...
Page 10
LED Dimming Mode 1: Change Intensity on ON/OFF Button Status LED Dimming Mode 2: Flash Intensity on ON Button Status Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Page [+] Feedback [+] Feedback ...
Page 11
LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions Note LED DIMMING is available only in CY8C20110. Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Page ...
Page 12
Register Map Register Name Address (in Hex) INPUT_PORT0 00 INPUT_PORT1 01 STATUS_POR0 02 STATUS_POR1 03 OUTPUT_PORT0 04 OUTPUT_PORT1 05 CS_ENABL0 06 CS_ENABLE 07 GPIO_ENABLE0 08 GPIO_ENABLE1 09 INVERSION_MASK0 0A INVERSION_MASK1 0B INT_MASK0 0C INT_MASK1 0D STATUS_HOLD_MSK0 0E STATUS_HOLD_MSK1 0F DM_PULL_UP0 ...
Page 13
Register Map (continued) Register Name Address (in Hex) OPR2_PRT0_02 29 OPR2_PRT1_02 2A OP_SEL_03 2B OPR1_PRT0_03 2C OPR1_PRT1_03 2D OPR2_PRT0_03 2E OPR2_PRT1_03 2F OP_SEL_04 30 OPR1_PRT0_04 31 OPR1_PRT1_04 32 OPR2_PRT0_04 33 OPR2_PRT1_04 34 OP_SEL_10 35 OPR1_PRT0_10 36 OPR1_PRT1_10 37 OPR2_PRT0_10 38 ...
Page 14
Register Map (continued) Register Name Address (in Hex) CS_DEBOUNCE 53 CS_NEG_NOISE_TH 54 CS_LOW_BL_RST 55 CS_FILTERING 56 CS_SCAN_POS_00 57 CS_SCAN_POS_01 58 CS_SCAN_POS_02 59 CS_SCAN_POS_03 5A CS_SCAN_POS_04 5B CS_SCAN_POS_10 5C CS_SCAN_POS_11 5D CS_SCAN_POS_12 5E CS_SCAN_POS_13 5F CS_SCAN_POS_14 60 CS_FINGER_TH_00 61 CS_FINGER_TH_01 62 ...
Page 15
Register Map (continued) Register Name Address (in Hex) [6] 7D SLEEP_PIN 7E SLEEP_CTRL 7F SLEEP_SA_CNTR 80 CS_READ_BUTTON 81 CS_READ_BLM 82 CS_READ_BLL 83 CS_READ_DIFFM 84 CS_READ_DIFFL 85 CS_READ_RAWM 86 CS_READ_RAWL 87 CS_READ_STATUSM 88 CS_READ_STATUSL 89 [6] 8A [6] 8B [6] 8C ...
Page 16
CapSense Express Commands [9] Command Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults ...
Page 17
Layout Guidelines and Best Practices CapSense Button Shapes Button Layout Design X: Button to ground clearance (Refer to Table 6 Y: Button to button clearance (Refer to Table 6 Recommended via Hole Placement Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 ...
Page 18
Table 6. Recommended Layout Guidelines and Best Practices Sl Category 1 Button Shape 2 Button Size 3 Button-Button Spacing 4 Button Ground Clearance 5 Ground Flood - Top Layer 6 Ground Flood - Bottom Layer 7 Trace Length from Sensor ...
Page 19
Example PCB Layout Design with Two CapSense Buttons and Two LEDs Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Figure 6. Top Layer Figure 7. Bottom Layer Page [+] Feedback [+] Feedback ...
Page 20
Operating Voltages 2 For details ACK time, refer to time is approximately four times the values mentioned in these tables. CapSense Constraints Parameter Parasitic Capacitance ( the P CapSense Sensor Overlay Thickness Supply Voltage ...
Page 21
Electrical Specifications Absolute Maximum Ratings Parameter Description T Storage temperature STG T Ambient temperature with power A applied V Supply voltage on V relative input voltage voltage applied to tristate IOZ ...
Page 22
DC General Purpose I/O Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<TA<85°C, 3.10V to 3.6V -40°C<TA<85°C. Typical parameters apply to 5V and 3.3V at 25°C ...
Page 23
DC Spec for I C Line with 1.8V External Pull Up This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.9V and 3.10V to 3.60V, and -40°C<TA <85°C, respectively. Typical parameters ...
Page 24
AC Electrical Specifications 5V and 3.3V AC General Purpose I/O Specifications Parameter Description TRise0 Rise time, strong mode, Cload = 50 pF, Port 0 TRise1 Rise time, strong mode, Cload = 50 pF, Port 1 TFall Fall time, strong mode, ...
Page 25
Figure 8. Definition of Timing for Fast/Standard Mode on the I Appendix- Examples of Frequently Used I Sl Requirement No. 1 Enter into setup mode 2 Enter into normal mode 3 Load factory defaults to RAM registers 4 Do ...
Page 26
Ordering Information Package Ordering Code Diagram CY8C20110-LDX2I 001-09116 CY8C20110-SX2I 51-85068 CY8C20180-LDX2I 001-09116 CY8C20180-SX2I 51-85068 CY8C20160-LDX2I 001-09116 CY8C20160-SX2I 51-85068 CY8C20140-LDX2I 001-09116 CY8C20140-SX2I 51-85068 CY8C20142-SX1I 51-85066 Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). ...
Page 27
Package Diagrams Figure 9. 16-Pin Chip On Lead (Sawn) (001-09116) Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 Figure 10. 16-Pin (150-Mil) SOIC (51-85068) CY8C20140/CY8C20142 Page [+] Feedback [+] Feedback ...
Page 28
Document Number: 001-54606 Rev. ** CY8C20110/CY8C20180/CY8C20160 Figure 11. 8-Pin (150-Mil) SOIC (51-85066) CY8C20140/CY8C20142 Page [+] Feedback [+] Feedback ...
Page 29
Document History Page Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142 CapSense Controllers Document Number: 001-54606 Orig. of Rev. ECN. Change ** 2741726 SLAN/FSU Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, ...