EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 84
EP1C20F
Manufacturer Part Number
EP1C20F
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1C20F.pdf
(106 pages)
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Cyclone Device Handbook, Volume 1
4–14
Preliminary
Internal timing parameters are specified on a speed grade basis
independent of device density.
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
CLR
PRE
CLKHL
SU
H
CO
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKHL
Table 4–25. LE Internal Timing Microparameters
Table 4–26. IOE Internal Timing Microparameters
Symbol
Symbol
1,234
1,234
Min
129
129
Min
348
280
280
29
12
—
—
—
—
—
—
—
0
-6
-6
1,130
1,135
2,627
2,615
Max
Max
173
454
511
—
—
—
—
—
—
—
—
—
—
Tables 4–25
1,562
1,562
Min
148
148
Min
400
322
322
33
13
—
—
—
—
—
—
—
0
-7
-7
through
1,299
1,305
3,021
3,007
Max
Max
198
522
587
—
—
—
—
—
—
—
—
—
—
1,818
1,818
4–28
Min
167
167
Min
452
364
364
37
15
—
—
—
—
—
—
—
0
Altera Corporation
show the
-8
-8
1,469
1,475
3,415
3,399
Max
Max
224
590
664
—
—
—
—
—
—
—
—
—
—
May 2008
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