EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 28
EP1C20F
Manufacturer Part Number
EP1C20F
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1C20F.pdf
(106 pages)
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Cyclone Device Handbook, Volume 1
2–22
Preliminary
4K
2K
1K
512
256
128
512
256
128
4K
2K
1K
512
256
512
256
Table 2–3. M4K RAM Block Configurations (Simple Dual-Port)
Table 2–4. M4K RAM Block Configurations (True Dual-Port)
Read Port
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
2
4
1
2
4
8
16
32
9
18
36
8
16
9
18
Port A
4K × 1 2K × 2 1K × 4 512 × 8
v
v
v
v
v
v
—
—
—
4K × 1
v
v
v
v
v
v
—
—
—
is not available in the true dual-port mode. Mixed-width configurations
are also possible, allowing different read and write widths.
and
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
v
v
v
v
v
—
—
2–4
v
v
v
v
v
v
—
—
—
summarize the possible M4K RAM block configurations.
2K × 2
v
v
v
v
v
—
—
v
v
v
v
v
v
—
—
—
1K × 4
v
v
v
v
v
—
—
256 × 16
Write Port
v
v
v
v
v
v
—
—
—
512 × 8
Port B
v
v
v
v
v
—
—
128 × 32
v
v
v
v
v
v
—
—
—
256 × 16
v
v
v
v
v
—
—
512 × 9 256 × 18 128 × 36
v
v
v
—
—
—
—
—
—
512 × 9
Altera Corporation
v
v
—
—
—
—
—
v
v
v
—
—
—
—
—
—
Tables 2–3
256 × 18
May 2008
v
v
—
—
—
—
—
v
v
v
—
—
—
—
—
—