AT84AD001BCTD ATMEL [ATMEL Corporation], AT84AD001BCTD Datasheet - Page 48

• Manufacturer Part Number: AT84AD001BCTD
• Description: Dual 8-bit 1 Gsps ADC
• Manufacturer: ATMEL [ATMEL Corporation]

Table 16. Definitions of Terms (Continued)
48
Abbreviation
ORT
PSRR
SFDR
SINAD
SNR
SSBW
TA
TC
TD1
TD2
TDO
TDR
TF
THD
TPD
TR
AT84AD001B
Definition
Overvoltage
Recovery Time
Power Supply
Rejection Ratio
Spurious Free
Dynamic Range
Signal to Noise and
Distortion Ratio
Signal to Noise
Ratio
Small Signal Input
Bandwidth
Aperture delay
Encoding Clock
period
Time Delay from
Data Transition to
Data Ready
Time Delay from
Data Ready to
Data
Digital Data Output
Delay
Data Ready Output
Delay
Fall Time
Total Harmonic
Distortion
Pipeline Delay
Rise Time
Description
The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on
the input is reduced to midscale
The ratio of input offset variation to a change in power supply voltage
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the highest spectral component (peak spurious spectral component). The peak
spurious component may or may not be a harmonic. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level)
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (-1
dBFS) to the RMS sum of all other spectral components including the harmonics, except DC
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first 9 harmonics
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -10 dB (-10 dBFS)
The delay between the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] and the time at which VIN and VINB are sampled
TC1 = minimum clock pulse width (high)
TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
The general expression is TD1 = TC1 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
The general expression is TD2 = TC2 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
The delay from the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
The delay from the falling edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
The time delay for the output data signals to fall from 20% to 80% of delta between the low
and high levels
The ratio expressed in dB of the RMS sum of the first 9 harmonic components to the RMS
input signal amplitude, set at 1 dB below full-scale. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level )
The number of clock cycles between the sampling edge of an input data and the associated
output data made available (not taking into account the TDO)
The time delay for the output data signals to rise from 20% to 80% of delta between the low
and high levels
2153C–BDC–04/04