AD7357_08 AD [Analog Devices], AD7357_08 Datasheet - Page 7

• Manufacturer Part Number: AD7357_08
• Description: Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
No.
1, 2
3, 6
4
5, 11
7, 8
9
10
12
13, 14
15
16
Mnemonic
V
REF
REFGND
AGND
V
V
CS
DGND
SDATA
SCLK
V
INA-
INB-
DD
DRIVE
A
, V
, V
, REF
INB+
INA+
B
, SDATA
B
A
Description
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 µF capacitor. Provided the output is buffered, the on-chip reference can be taken from
these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and
appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for
the external reference is 2.048 V +100 mV to V
Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between this
pin and the REF
Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input signals
and should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
Power Supply Input. The V
a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7357
and framing the serial data transfer.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should connect
to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the
AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both
ADCs. The data stream consists of one leading zero followed by the 14 bits of conversion data followed by a
trailing zero. The data is provided MSB first. If CSis held low for 18 SCLK cycles rather than 16, then two further
trailing zeros appear after the 14 bits of data. If CSis held low for a further 18 SCLK cycles on either SDATA
SDATA
conversion on both ADCs to be gathered in serial format on either SDATA
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This
clock is also used as the clock source for the conversion process.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at V
B
, the data from the other ADC follows on the SDATA pin. This allows data from a simultaneous
A
and REF
REFGND
B
DD
pins.
AGND
REF
REF
V
V
V
V
INA+
INB+
INA–
INB–
range for the AD7357 is 2.5 V ± 10%. The supply should be decoupled to AGND with
A
B
1
4
2
3
5
6
7
8
Rev. PrF | Page 7 of 20
(Not to Scale)
AD7357
TOP VIEW
Figure 2.
DD
.
16
15
14
13
12
11
10
9
V
SCLK
SDATA
SDATA
DGND
AGND
CS
V
DRIVE
DD
A
B
A
or SDATA
B
.
DD
.
AD7357
A
or