AD7357_08 AD [Analog Devices], AD7357_08 Datasheet - Page 18

• Manufacturer Part Number: AD7357_08
• Description: Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
• Manufacturer: AD [Analog Devices]

AD7357
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial
interfacing to the AD7357. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7357 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode at
which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 16 SCLKs to complete. Once 15
SCLK falling edges have elapsed, the track and hold goes back
into track on the next SCLK rising edge, as shown in Figure 30
at Point B. On the rising edge of CS , the conversion will be
terminated and SDATA
If CS is not brought high, but is instead held low for a further
16 SCLK cycles on SDATA
ADCB are output on SDATA
Likewise, if CS is held low for a further 16 SCLK cycles on
SDATA
SDATA
A
B
D
, the data from the conversion on ADC A is output on
(see Figure 31). In this case, the SDATA line in use
SCLK
OUT
CS
D
D
A
SCLK
OUT
OUT
THREE-
STATE
CS
A
B
THREE-
STATE
t
2
2 LEADING
0
ZEROS
A
1
2 LEADING ZEROS
t
and SDATA
t
3
2
0
A
0
, the data from the conversion on
A
1
.
t
2
DB13
3
0
A
2
B
3
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
DB13
DB12
go back into three-state.
A
4
3
DB11
DB12
t
t
6
4
A
t
Figure 30. Serial Interface Timing Diagram
5
5
4
DB11
t
t
6
4
15
t
CONVERT
Rev. PrF | Page 18 of 20
t
5
DB0
7
DB10
2 ZEROS
t
7
A
16
0
17
goes back into three-state on the 32
rising edge of CS , whichever occurs first.
A minimum of 16 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7357. CS going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 14-bit
result then follows with the final bit in the data transfer valid on
the 16
(15
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the CS
falling edge would have the second leading zero provided, and
the 15
0
th
DB2
) falling edge. In applications with a slower SCLK, it may be
th
th
18
DB13
falling edge, having being clocked out on the previous
rising SCLK edge would have DB0 provided.
t
B
5
DB1
DB12
B
15
Preliminary Technical Data
DB0
16
B
DB1
0
B
t
8
t
ACQUISITION
31
DB0
nd
THREE-STATE
SCLK falling edge or the
t
B
QUIET
t
32
9
0
THREE-
STATE