74LVC2G74DP NXP [NXP Semiconductors], 74LVC2G74DP Datasheet

74LVC2G74DP

Manufacturer Part Number

74LVC2G74DP

Description

Single D-type flip-flop with set and reset; positive edge trigger

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.74LVC2G74DP.pdf (19 pages)

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1. General description

2. Features

The 74LVC2G74 is a single positive edge triggered D-type ﬂip-ﬂop with individual data (D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully speciﬁed for partial power down applications using I

circuitry disables the output, preventing damaging backﬂow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

74LVC2G74

Single D-type ﬂip-ﬂop with set and reset; positive edge trigger

Rev. 03 — 9 August 2007

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

ESD protection:

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Speciﬁed from 40 C to +85 C and 40 C to +125 C

24 mA output drive (V

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

= 3.0 V)

Product data sheet

OFF

. The I

OFF

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