PCF85133U/2DA/1 NXP [NXP Semiconductors], PCF85133U/2DA/1 Datasheet - Page 19

• Manufacturer Part Number: PCF85133U/2DA/1
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF85133_1
Product data sheet
7.16.3 Acknowledge
7.16.4 I
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse.
Acknowledgement on the I
The PCF85133 acts as an I
transmit data to an I
the acknowledge signals from the selected devices. Device selection depends on the
I
subaddress.
In a single device application, the hardware subaddress inputs A0, A1 and A2 are
normally tied to V
applications A0, A1 and A2 are tied to V
scheme such that no two devices with a common I
hardware subaddress.
2
2
Fig 14. Acknowledgement on the I
•
•
•
•
C-bus slave address, on the transferred command data and on the hardware
C-bus controller
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
by transmitter
data output
by receiver
data output
SCL from
master
SS
2
condition
which defines the hardware subaddress 0. In multiple device
C-bus master receiver. The only data output from the PCF85133 are
START
Rev. 1 — 17 February 2009
S
2
C-bus is shown in
2
C-bus slave receiver. It does not initiate I
1
2
C-bus
SS
Universal LCD driver for low multiplex rates
or V
Figure
2
DD
in accordance with a binary coding
2
C-bus slave address have the same
14.
not acknowledge
acknowledge
8
PCF85133
acknowledgement
2
clock pulse for
C-bus transfers or
© NXP B.V. 2009. All rights reserved.
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