pcf85133 NXP Semiconductors, pcf85133 Datasheet
pcf85133
Related parts for pcf85133
pcf85133 Summary of contents
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... Rev. 1 — 17 February 2009 1. General description The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications ...
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... GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR FF SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85133 PCF85133_1 Product data sheet Description bare die; 110 bumps; 4.16 1.07 Marking codes BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCF85133 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Top view. For mechanical details, see Fig 2. Pinning of PCF85133 6.2 Pin description Table 3. Symbol SDAACK SDA SCL CLK V DD SYNC OSC FF A0, A1 and A2 SA0 LCD BP2, BP0, BP3 and BP1 S0 to S79 PCF85133_1 Product data sheet ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF85133 depend on the required number of active backplane outputs. A selection of display configurations is shown in All of the display configurations can be implemented in a typical system as shown in Figure 3 ...
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... NXP Semiconductors 7.1 Power-on reset At power-on the PCF85133 resets to the following starting conditions: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • Blinking is switched off • Input and output bank selectors are reset • ...
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... V = --------------------- - 2 LCD LCD off RMS is sometimes referred as the LCD operating voltage. LCD Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates 2 and is determined from the equation: off(RMS) 1.732 1.528 2.449V = off RMS off RMS 3 2.309V = off RMS ...
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... LCD V ( (t) V (t). state2 (Sn+1) BP0 off(RMS) Static drive mode waveforms Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) mgl745 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85133 allows the use of Figure 6. Fig 5. PCF85133_1 Product data sheet 1 1 bias LCD BP0 LCD LCD BP1 LCD LCD ...
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... V (t) V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms mgl747 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 mgl748 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates T fr state 1 state 2 mgl749 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. LCD segments ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency f which either is derived from the built-in oscillator frequency clk or equals an external clock frequency clk 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to V from pin CLK provides the clock signal for cascaded PCF85133s in the system ...
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... RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF85133 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands ...
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... The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs; and between the bits in a RAM word and the backplane outputs. Display RAM bitmap Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates 75 76 ...
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LCD segments LCD backplanes S a n+2 b BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... In static mode, row 0 is selected The PCF85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1 ...
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... The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCF85133, the SDA line becomes fully 2 I C-bus compatible ...
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... Product data sheet SDA SCL data line stable; data valid S START condition MASTER SLAVE TRANSMITTER/ TRANSMITTER/ RECEIVER RECEIVER Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Figure 11). change of data allowed mba607 Figure 12. P STOP condition SLAVE MASTER TRANSMITTER/ ...
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... C-bus 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCF85133 are which defines the hardware subaddress 0. In multiple device SS Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Figure 14 ...
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... Two I C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85133. The least significant bit of the slave address is bit R/W. The PCF85133 is a write-only device and will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defi ...
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... Symbol Value Description CO continue bit 0 last control byte 1 control bytes continue RS register selection 0 command register 1 data register - not relevant Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates COMMAND RAM DATA A RAM DATA LSB ...
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... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF85133 are defined in Table 9. Command mode-set load-data-pointer device-select bank-select blink-select Table 10. Bit [1] The possibility to disable the display allows implementation of blinking under external control. ...
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... RAM banks BF[1:0] blink mode selection 00 off Table 7. Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates [1] Section 7.13 and Section 7.14. 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [1] [2] © ...
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... Product data sheet V DD FF, A0, A1 LCD BP0, BP1, BP2, BP3 S79 V SS Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates SCL, SDA, SDAACK LCD V SS © NXP B.V. 2009. All rights reserved. ...
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... LCD supply current total power dissipation power dissipation per output electrostatic discharge voltage latch-up current storage temperature Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD ...
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... 100 - 100 - [3] - 1.5 [3] - 6.0 2 C-bus inactive. PCF85133 Max Unit 5.5 V 6 5.5 V 5 +100 mV +100 13.5 k © NXP B.V. 2009. All rights reserved. ...
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... Figure 19. PCF85133_1 Product data sheet = 2 6 +85 C; unless otherwise specified. LCD amb f clk f = --------- . Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Conditions Min Typ [1][ 1440 1970 DD [1][ 1920 2640 ...
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... CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA C-bus timing waveforms Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates t clk( HD;DAT t HIGH t SU;STA © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations sixteen PCF85133s can be recognized on the 2 same I programmable I Table 18. Cluster 1 2 When cascaded PCF85133s are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display ...
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... A PCF85133 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF85133 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC ...
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... NXP Semiconductors Fig 21. Synchronization of the cascade for the various PCF85133 drive modes PCF85133_1 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. ...
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... Bare die description 13.1 General description Table 20. Type number PCF85133U/2DA/1 [1] Pressure of diamond head 13.2 Alignment marks Fig 22. Alignment marks of PCF85133 Table 21. Symbol S1 C1 13.3 Bump locations Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see ...
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... Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Description supply voltage cascade synchronization input/output oscillator select frame frequency select subaddress input 2 I C-bus slave address input; bit 0 ground supply voltage ...
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... Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Description LCD segment output © NXP B.V. 2009. All rights reserved ...
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... SS Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Description LCD segment output LCD backplane output dummy pad Section 7.16. © NXP B.V. 2009. All rights reserved ...
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... max 0.018 mm nom 0.380 0.015 0.0338 4.156 1.069 0.054 0.2026 min 0.012 Note 1. Dimension not drawn to scale. Outline version IEC PCF85133 - - - Fig 23. Bare die outline of PCF85133 PCF85133_1 Product data sheet PC85133 detail scale (1) (1) (1) D ...
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... All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or equivalent standards. 16. Packing information y Fig 24. Tray details for PCF85133 PCF85133_1 Product data sheet 1.1 2.1 3.1 1 ...
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... NXP Semiconductors Fig 25. Tray alignment for PCF85133 tray Table 23. See Figure Symbol The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray (see Refer to the bump location diagram name on the die surface ...
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... Liquid Crystal Display Machine Model Random Access Memory Resistance and Capacitance Root Mean Square Data sheet status Product data sheet Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates Change notice Supersedes - - © NXP B.V. 2009. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 1 — 17 February 2009 PCF85133 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
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... Bare die description . . . . . . . . . . . . . . . . . . . . 32 General description . . . . . . . . . . . . . . . . . . . . 32 Alignment marks . . . . . . . . . . . . . . . . . . . . . . 32 Bump locations Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 36 Handling information . . . . . . . . . . . . . . . . . . . 37 Packing information . . . . . . . . . . . . . . . . . . . . 37 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39 Legal information . . . . . . . . . . . . . . . . . . . . . . 40 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Contact information . . . . . . . . . . . . . . . . . . . . 40 Contents Date of release: 17 February 2009 Document identifier: PCF85133_1 All rights reserved. ...