PCF2119AU/2DA/2 NXP [NXP Semiconductors], PCF2119AU/2DA/2 Datasheet - Page 63

• Manufacturer Part Number: PCF2119AU/2DA/2
• Description: LCD controllers/drivers
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 42.
[1]
[2]
PCF2119X_5
Product data sheet
Step
16
17
18
19
20
21
22
23
24
25
26
27
28
X = don’t care.
SDA is left at high-impedance by the microcontroller during the read acknowledge.
I
Write_data to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
optional l
I
slave address for write
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS
0
control byte
CO
1
Return_home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
I
slave address for read
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack PHILIPS
0
control byte for read
CO
0
Read_data: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
X
Read_data: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
Read_data: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS
0
I
2
2
2
2
C-bus byte
C-bus start
C-bus start
C-bus STOP
Example of I
1
1
RS
0
0
1
RS
1
X
1
1
2
C-bus STOP
0
1
0
0
0
1
0
1
X
0
0
2
C-bus operation; 1-line display (using external reset, assuming pin SA0 = V
SCL + master acknowledge
SCL + master acknowledge
SCL + no master acknowledge
1
1
0
0
0
1
0
0
X
0
0
0
0
0
0
0
0
0
0
X
1
1
0
1
0
0
0
1
0
0
X
0
0
1
0
0
0
1
0
0
0
X
0
0
Rev. 05 — 13 August 2009
1
0
0
0
0
1
0
0
X
0
1
[2]
[2]
[2]
1
1
Ack PHILIPS
1
1
1
Ack PHILIPS
1
0
0
1
Display
PHILIPS
PHILIPS
PHILIPS
PHILIPS
Operation
writes ‘S’
sets DDRAM address 0 in address counter
(also returns shifted display to original
position; DDRAM contents unchanged); this
instruction does not update the data register
during the acknowledge cycle the content of
the data register is loaded into the internal
I
previous instruction neither a ‘set address’
nor a Read_data has been performed;
therefore the content of the data register
was unknown; bit R/W has to be set to logic
1 while still in I
DDRAM content will be read from following
instructions
8
during previous acknowledge cycle is
shifted out over SDA; MSB is DB7; during
master acknowledge content of DDRAM
address 01 is loaded into the I
interface
8
during master acknowledge code of ‘I’ is
loaded into the I
no master acknowledge; after the content of
the I
no internal action is performed; no new data
is loaded to the interface register, data
register is not updated, address counter is
not incremented and cursor is not shifted
2
C-bus interface to be shifted out; in the
SCL; content loaded into interface
SCL; code of letter ‘H’ is read first;
2
C-bus interface register is shifted out
2
C-write mode
2
C-bus interface
LCD controllers/drivers
PCF2119x
© NXP B.V. 2009. All rights reserved.
SS
)
2
[1]
C-bus
…continued
63 of 79