ADF4351BCPZ AD [Analog Devices], ADF4351BCPZ Datasheet - Page 12

• Manufacturer Part Number: ADF4351BCPZ
• Description: Wideband Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4351
MUXOUT AND LOCK DETECT
The multiplexer output on the
various internal points on the chip. The state of MUXOUT is
controlled by the M3, M2, and M1 bits in Register 2 (see Figure 26).
Figure 19 shows the MUXOUT section in block diagram form.
INPUT SHIFT REGISTERS
The
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. As shown in Figure 2, the control bits are the three LSBs:
DB2, DB1, and DB0. Table 6 shows the truth table for these bits.
Figure 23 summarizes how the latches are programmed.
Table 6. Truth Table for the C3, C2, and C1 Control Bits
C3
0
0
0
0
1
1
ANALOG LOCK DETECT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
ADF4351
N DIVIDER OUTPUT
Control Bits
RESERVED
C2
0
0
1
1
0
0
digital section includes a 10-bit RF R counter,
DGND
DV
DD
Figure 19. MUXOUT Schematic
C1
0
1
0
1
0
1
MUX
ADF4351
CONTROL
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
allows the user to access
DGND
DV
DD
MUXOUT
Rev. 0 | Page 12 of 28
PROGRAM MODES
Table 6 and Figure 23 through Figure 29 show how the program
modes are set up in the ADF4351.
The following settings in the
value, modulus value, reference doubler, reference divide-by-2,
R counter value, and charge pump current setting. Before the part
uses a new value for any double-buffered setting, the following
two events must occur:
1.
2.
For example, any time that the modulus value is updated,
Register 0 (R0) must be written to, to ensure that the modulus
value is loaded correctly. The divider select value in Register 4
(R4) is also double buffered, but only if the DB13 bit of
Register 2 (R2) is set to 1.
VCO
The VCO core in the
each of which uses 16 overlapping bands, as shown in Figure 20,
to allow a wide frequency range to be covered without a large
VCO sensitivity (K
ious performance.
The correct VCO and band are selected automatically by the
VCO and band select logic at power-up or whenever Register 0
(R0) is updated.
VCO and band selection take 10 PFD cycles multiplied by the
value of the band select clock divider. The VCO V
nected from the output of the loop filter and is connected to an
internal reference voltage.
The new value is latched into the device by writing to the
appropriate register.
A new write is performed on Register 0 (R0).
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
2.5
V
Figure 20. V
) and resultant poor phase noise and spur-
ADF4351
FREQUENCY (GHz)
3.0
ADF4351
TUNE
consists of three separate VCOs,
vs. Frequency
3.5
are double buffered: phase
Data Sheet
4.0
TUNE
is discon-
4.5