MT48LC128M4A2_07 MICRON [Micron Technology], MT48LC128M4A2_07 Datasheet - Page 35

• Manufacturer Part Number: MT48LC128M4A2_07
• Description: 512Mb x4, x8, x16 SDRAM
• Manufacturer: MICRON [Micron Technology]

Concurrent Auto Precharge
READ with Auto Precharge
Figure 28:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Internal
States
READ with Auto Precharge Interrupted by a READ
COMMAND
Note:
ADDRESS
BANK m
BANK n
CLK
An access command to (READ or WRITE) another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
DQ
rupt a READ on bank n, CL later. The PRECHARGE to bank n will begin when the
READ to bank m is registered (see Figure 28).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (see Figure 29 on page 36).
DQM is LOW.
Page Active
T0
NOP
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
READ with Burst of 4
CL = 3 (BANK n)
T2
NOP
35
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
READ with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
CL = 3 (BANK m)
NOP
D
OUT
a
t
RP - BANK n
Transitioning Data
T5
NOP
D
a + 1
512Mb: x4, x8, x16 SDRAM
OUT
T6
NOP
D
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OUT
d
Idle
Don’t Care
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT
Operations