AD71028JST AD [Analog Devices], AD71028JST Datasheet - Page 12

• Manufacturer Part Number: AD71028JST
• Description: Dual Digital BTSC Encoder with Integrated DAC
• Manufacturer: AD [Analog Devices]

AD71028
SPI PORT
OVERVIEW
The AD71028 can be controlled using the SPI port. In general,
there are three parameters per processor that can be controlled:
the encoder output level, the Phat Stereo image enhancement
algorithm, and the dialog enhancement algorithm. It is also
possible to write new data into the parameter RAM to alter the
filter coefficients used in the BTSC encoding process. This is a
fairly complex topic unnecessary for normal operation of the
chip, and the details are not included in this data sheet. Please
contact ADI if modifications to the BTSC filters are required.
The SPI port uses a 4-wire interface consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches the serial input data on a
low-to-high transition. The CDATA signal carries the serial
input data, and the COUT signal is the serial output data. The
Table 11. SPI Port Address Decoding
SPI Address
0–255
256
257
258
259
260
512–767
768
769
770
771
772
CLATCH
CDATA
CCLK
CLATCH
CDATA
CCLK
COUT
Register Name
Parameter RAM Processor A
SPI Control Register Processor A
Reserved
Output Level Processor A
Stereo Spreading Control Processor A
Dialog Enhancement Control Processor A
Parameter RAM Processor B
SPI Control Register Processor B
Reserved
Output Level Processor B
Stereo Spreading Control Processor B
Dialog Enhancement Control Processor B
BYTE 0
HI-Z
Figure 5. Sample of SPI Write Format (Single-Write Mode)
Figure 6. Sample of SPI Read Format (Single-Read Mode)
BYTE 0
BYTE 1
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DATA
BYTE 1
COUT signal remains three-stated until a READ operation is
requested. This allows other SPI compatible peripherals to share
the same readback line. All SPI transactions follow the same
basic format, shown in Figure 5. Figure 6 shows the read format.
The Wb/R bit is low for a write and high for a read operation.
The 10-bit address word is decoded into either a location in the
parameter RAM or one of the SPI registers. The number of data
bytes varies according to the register or memory being accessed.
The detailed data format diagram for continuous-mode
operation is given in the SPI Read/Write Data Formats section.
SPI ADDRESS DECODING
Table 11 shows the address decoding used in the SPI port. The
SPI address space encompasses a set of registers and the param-
eter RAM. The parameter RAM is loaded on power-up from an
on-board boot ROM.
DATA
XXX
Read/Write Word Length
Write: 22 Bits, Read: 22 Bits
Write: 11 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: 22 Bits
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
DATA
BYTE 4
HI-Z