MBM29F400BC-55PF SPANSION [SPANSION], MBM29F400BC-55PF Datasheet - Page 21

• Manufacturer Part Number: MBM29F400BC-55PF
• Description: FLASH MEMORY CMOS 4M (512K x 8/256K x 16) BIT
• Manufacturer: SPANSION [SPANSION]

20
MBM29F400TC
RESET
Hardware Reset
Byte/Word Configuration
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
The MBM29F400TC/BC device may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
device requires time of t
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET/RY/BY Timing
Diagram” in TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TC/BC device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE
Timing Diagram for Write Operations” in TIMING DIAGRAM for the timing diagram.
The MBM29F400TC/BC are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporate several features to prevent inadvertent write cycles resulting form V
power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the device with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
0
CC
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ
CC
Write Inhibit
level is greater than V
RH
before it will allow read access. When the RESET pin is low, the device will be in the
LKO
CC
-55/-70-90
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
IL
, the command register is disabled and all internal program/erase circuits
CC
) for at least 500 ns in order to properly reset the internal state machine.
14
is above 3.2 V.
to DQ
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
8
IL
bits are tri-stated. However, the command bus cycle is always
/MBM29F400BC
, CE = V
IH
will not accept commands on the rising edge of WE.
7
IH
to DQ
, or WE = V
0
and the DQ
IH
. To initiate a write cycle CE and WE
IL
. The RESET pin has a pulse
15
to DQ
-55/-70-90
8
bits are ignored. Refer
CC
power-up and
15
/A
CC
-1
pin
15
less
to