MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 44

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
6.2.2 QPSK Status. Registers 4 - 5 (R)
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
B7:
B6:
B5-0:
6.2.3 Symbol Rate Output. Registers 116 - 117 (R)
SYM RAT OP[15:0] These two bytes contain a positive number that is inversely proportional to the Symbol rate.
The decimation ratio index must also be read from the MONITOR register bits B[7:5] and divided by 32 to
normalise the result.
Rs =
Where: Rs = Symbol rate in MBaud
44
SYM RAT OP H
SYM RAT OP L
QPSK STAT H
QPSK STAT L
NAME
NAME
NAME
----------------------------------------------------------
SYM_RAT_OP+ 8192
High = QPSK SNR MSB
High = QPSK SNR LSB
High = QPSK FR LOCK
High = QPSK Timing AGC LOCK
High = QPSK Timing LOCK
High = QPSK Carrier LOCK
High = QPSK Carrier and Timing (CT) Lock
High = QPSK LOCK
High = QPSK Timing sweep on
High = QPSK Carrier sweep on
Reserved
PLL CLK = PLL clock frequency in MHz
SYM RAT OP = value of registers 116 and 117.
DEC RATIO = MONITOR H[7:5] when MON CTRL[2:0] = 5.
PLL_CLK *8192
QPSK Demodulator
ADR
ADR
ADR
116
117
04
05
* 2 -DEC RATIO
B7
B7
B7
SYM RAT OP[15:8] Symbol Rate Output (high byte)
SYM RAT OP[7:0] Symbol Rate Output (low byte)
B6
B6
B6
QPSK STATUS[15:8] (high byte)
QPSK STATUS[7:0] (low byte)
B5
B5
B5
B4
B4
B4
B3
B3
B3
B2
B2
B2
B1
B1
B1
B0
B0
B0
R
R
R
R
Def
hex
Def
hex
Def
hex
00
00
00
00