MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 21

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.4 Spectral Inversion
Spectral inversion of the QPSK signal can be caused
by the transmitter or the receiver front-end. In the
latter case, this could happen due to the way I-Q
conversion is carried out or because the I and Q
wires are swapped between the I-Q converter and
the MT312. If spectral inversion is caused by the
receiver front-end, then this must be removed by
swapping I and Q (within MT312) before QPSK
demodulation, by setting Q IQ SP bit B6 of QPSK
CTRL register (26) to 1.
3.5 MT312 Initialisation Read/Write Registers
3.5.1 Reset. Register 21 (R/W)
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
Writing a one to these register locations generates a reset pulse three crystal clock periods wide.
The register automatically resets to zero after use.
A full reset does reset the registers to their default values.
A partial reset does not reset the registers to their default values.
RESET
NAME
FR 312
PR 312
FR QP
PR QP
FR VIT
PR VIT
PR BA
PR DS
ADR
21
High = Full reset of MT312 device.
High = Partial reset of MT312 device.
High = Full reset of QPSK block.
High = Partial reset of QPSK block.
High = Full reset of Viterbi block.
High = Partial reset of Viterbi block.
High = Partial reset of Byte Align block.
High = Partial reset of De-scrambler block.
312
B7
FR
312
PR
B6
QP
B5
FR
If no spectral inversion is caused by the receiver
front-end design, then bit B6 of QPSK CTRL must
always be held at zero. If the transmitted signal is
known to be spectrally inverted, then V IQ SP bit B6
of the VIT MODE register (25) must be set to 1. Then
I and Q are swapped after QPSK demodulation. If
the spectral inversion status of the transmitted signal
is not known, then after QPSK has locked (i.e. QPSK
CT LOCK = 1), the software must try to achieve FEC
lock with the bit B6 of VIT MODE register first at zero
and then at one.
PR
QP
B4
VIT
FR
B3
VIT
PR
B2
Initialisation
PR
B1
BA
PR
DS
B0
R/W
MT312
hex
Def
00
21