MC68HC11E Motorola, MC68HC11E Datasheet - Page 159

• Manufacturer Part Number: MC68HC11E
• Description: Microcontrollers
• Manufacturer: Motorola

9.5.3 Pulse Accumulator Control Register
9.6 Computer Operating Properly (COP) Watchdog Function
M68HC11E Family — Rev. 5
MOTOROLA
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits
control the pulse accumulator and IC4/OC5 functions.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
The clocking chain for the COP function, tapped off of the main timer divider chain,
is only superficially related to the main timer system. The CR[1:0] bits in the
OPTION register and the NOCOP bit in the CONFIG register determine the status
of the COP function. One additional register, COPRST, is used to arm and clear
the COP watchdog reset system. Refer to
more detailed discussion of the COP function.
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
These two bits determine the rate at which the RTI system requests interrupts.
The RTI system is driven by an E divided by 2
so it is independent of the timer prescaler. These two control bits select an
additional division factor. Refer to
Address:
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9-23. Pulse Accumulator Control Register (PACTL)
DDRA7
Section 6. Parallel Input/Output (I/O)
9.7 Pulse
9.7 Pulse
9.7 Pulse
Section 6. Parallel Input/Output (I/O)
9.7 Pulse
$1026
Bit 7
0
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PAEN
Accumulator.
Accumulator.
Accumulator.
Accumulator.
6
0
Timing System
PAMOD
Computer Operating Properly (COP) Watchdog Function
5
0
Table
PEDGE
4
0
Section 5. Resets and Interrupts
9-5.
DDRA3
13
3
0
rate clock that is compensated
Ports.
Ports.
I4/O5
2
0
RTR1
1
0
Timing System
Data Sheet
RTR0
Bit 0
0
for a
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