ADE7754 Analog Devices, ADE7754 Datasheet - Page 23

• Manufacturer Part Number: ADE7754
• Description: Poly-phase Multi-Function Energy Metering IC with Serial Port
• Manufacturer: Analog Devices

Integration times under steady load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 0.4µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
Watt Gain registers set to 000h, the average word value from
each LPF2 is D1B717h - see Figures 20 and 22. The
maximum value which can be stored in the Active Energy
register before it over flows is 2
average word value is added to the internal register, which can
store 2
the integration time under these conditions with WDIV=0 is
calculated as follows:
When WDIV is set to a value different from 0, the integration
time varies as shown on Equation 10.
Time = Time
The WDIV register can be used to increase the time before
the active energy register overflows, therefore reducing the
communication needs with the ADE7754.
Energy to Frequency Conversion
The ADE7754 also provides energy to frequency conversion
for calibration purposes. After initial calibration at manufac-
ture, the manufacturer or end customer will often verify the
energy meter calibration. One convenient way to verify the
meter calibration is for the manufacturer to provide an output
frequency which is proportional to the energy or active power
under steady load conditions. This output frequency can
provide a simple, single wire, optically isolated interface to
external calibration equipment. Figure 27 illustrates the
Energy to frequency conversion in the ADE7754.
Active Power
Phase A
Active Power
Phase B
Active Power
Phase C
A Digital to Frequency Converter (DFC) is used to generate
the CF pulsed output. The DFC generates a pulse each time
one LSB in the Active Energy register is accumulated. An
output pulse is generated when CFDEN/CFNUM pulses are
generated at the DFC output. Under steady load conditions
the output frequency is proportional to the Active Power.
The maximum output frequency (CFNUM=00h &
CFDEN=00h) with full scale AC signals on the three phases
i.e. current channel and voltage channel is approximately
96kHz.
The ADE7754 incorporates two registers to set the frequency
of CF (CFNUM[11:0] and CFDEN[11:0]). These are
unsigned 12-bit registers which can be used to adjust the
frequency of CF to a wide range of values. These Frequency
scaling registers are 12-bit registers which can scale the
output frequency by 1/2
REV. PrG 01/03
Time
Figure 27– ADE7754 Energy to Frequency Conversion
=
53
1
F FFFF FFFF FFFFh
- 1 or 1F,FFFF,FFFF,FFFFh before it overflows,
+
,
Σ
+
3
WDIV=0
×
53
,
D B
Total Active
Power
1 717
x WDIV
12
,
to 1 with a step of 1/2
h
0
PRELIMINARY TECHNICAL DATA
23
DFC
×
-1
0 4
. µ
or 7F,FFFFh. As the
11
11
s
CFNUM[11:0]
CFDEN[11:0]
=
88
(10)
12
s
.
0
0
CF
–23–
If the value zero is written to any of these registers, the value
one would be applied to the register. The ratio CFNUM/
CFDEN should be smaller than one to assure proper opera-
tion. If the ratio of the registers CFNUM/CFDEN is greater
than one, the CF frequency can no longer be guaranteed to
be a consistent value.
For example if the output frequency is 18.744kHz while the
contents of CFDEN are zero (000h), then the output frequency
can be set to 6.103Hz by writing BFFh to the CFDEN
register.
The output frequency will have a slight ripple at a frequency
equal to twice the line frequency. This is due to imperfect
filtering of the instantaneous power signal to generate the
Active Power signal – see ACTIVE POWER CALCULATION.
Equation 5 gives an expression for the instantaneous power
signal. This is filtered by LPF2 which has a magnitude
response given by Equation 11.
The Active Power signal (output of the LPF2) can be
rewritten as.
where f
From Equation 8
From Equation 13 it can be seen that there is a small ripple
in the energy calculation due to a sin(2ωt) component. This
is shown graphically in Figure 28. The ripple will get larger
as a percentage of the frequency at larger loads and higher
output frequencies. Choosing a lower output frequency at CF
for calibration can significantly reduce the ripple. Also
averaging the output frequency by using a longer gate time for
the counter will achieve the same results.
E t
p t
H f
( )
( )
( ) =
=
=
VI
VIt
l
is the line frequency (e.g., 60Hz)
−
E(t)
−







1
Figure 28 – Output frequency ripple







+
4
1
1
π
+
8
f
VI
f

 
2
l
2
2
8
1
f
VI
l
+

 
2

 







2
⋅
8
t
cos
f
VIt
l
−

 







2
(
4
4







π
π
⋅
f
l
sin
f t
1
l
VI
+
(
4
)



π
2
8
f
l



f t
2
l







⋅
ADE7754
)
sin
(
4
π
f
l
t
(13)
)
(11)
(12)