ADE7754 Analog Devices, ADE7754 Datasheet
ADE7754
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ADE7754 Summary of contents
Page 1
... This signal is also useful for synchronization of relay switching. Data is read from the ADE7754 via the SPI serial interface. The interrupt request output (IRQ open drain, active low logic output. The IRQ output will go active low when one or more interrupt events have occurred in the ADE7754 ...
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... Uncalibrated error, see Terminology for detail External 2.5V reference External 2.5V reference 2.4V +8% 2.4V -8% Calibrated DC offset DV =5V ± =5V ± Typical 10nA, Vin= DVDD=5V ± 5% DVDD=5V ± 5% For specified performance + +5% ORDERING GUIDE PACKAGE OPTION RW-24 RW-24 in Reel ADE7754 Evaluation Board ...
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... PRELIMINARY TECHNICAL DATA ADE7754 TIMING CHARACTERISTICS Units Write timing (min (min (min (min (min 400 ns (min (min 100 ns (min) 8 Read timing µs (min ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... TPC 2. Real Power Error as a percent of reading over Power Factor with Internal reference (DELTA connection) TBD TPC 4. Real Power Error as a percent of reading over Power Factor with Internal reference (Gain = 4) TBD TPC 6. Voltage rms Error as a percent of reading with Internal reference (Gain = 1) – 5 – ADE7754 ...
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... PRELIMINARY TECHNICAL DATA ADE7754 TBD TPC 7. Real Power Error as a percent of reading over Power Factor with External reference (Gain = 1) TBD TPC 9. Real Power Error as a percent of reading over input frequency with Internal reference TBD TPC 11. Real Power Error as a percent of reading over ...
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... PRELIMINARY TECHNICAL DATA TBD TPC 13. Current Channel offset distribution (Gain = 1) REV. PrG 01/03 TBD TPC 14. Current Channel offset distribution (Gain = 4) – 7 – ADE7754 ...
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... All inputs have internal ESD protection circuitry, and in addition an over voltage of ±6V can be sustained on these inputs without risk of permanent damage. 17 RESET Reset pin for the ADE7754. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface reset condition. 18 IRQ Interrupt Request Output ...
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... ADE7754. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used Chip Select. Part of the four wire Serial Interface. This active low logic input allows the ADE7754 to share the serial bus with several other devices. See ADE7754 Serial Inter- face Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK— ...
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... The ADE7754 also contains an on-chip power supply moni- tor. The Analog Supply ( continuously monitored DD by the ADE7754. If the supply is less than 4V ± 5% then the ADE7754 will inactive state, i.e. no energy will be accumulated when the supply voltage is below 4V. This is useful to ensure correct device operation at power up and during power down ...
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... The first is oversampling. By over sampling we mean that the signal is sampled at a rate (frequency) which is many times higher than the bandwidth of interest. For example the sampling rate in the ADE7754 is CLKIN/12 (833kHz) and the band of interest is 40Hz to 2kHz. Oversampling has the effect of spreading the quanti- zation noise (noise due to sampling) over a wider bandwidth ...
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... Mask register to logic one, the interrupt request output IRQ will go active low when a sample is available. The timing is shown in Figure 9. The 24-bit waveform samples are trans- ferred from the ADE7754 one byte (8-bits time, with the most significant byte shifted out first. IRQ ...
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... The upper byte is instead filled with zeros. 24-bit D817h waveform samples are transferred from the ADE7754 one byte (8-bits time, with the most significant byte shifted 2838h out first. The timing is the same as that for the current channels and is shown in Figure 9 ...
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... Interrupt Mask register), the IRQ logic output will go active low - see ADE7754 Interrupts. All the phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. Sag Level Set ...
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... PRELIMINARY TECHNICAL DATA PEAK DETECTION The ADE7754 can also be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value. Figure 15 illustrates the behavior of the PEAK detection for the voltage channel VPEAK[7:0] ...
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... The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7754 provides a means of digitally calibrating these small phase errors. The ADE7754 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for small phase errors. Because the compensa- tion is in time, this technique should only be used for small phase errors in the range of 0.1° ...
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... N 1 ∑ = ⋅ rms The method used to calculate the RMS value in the ADE7754 is to low-pass filter the square of the input signal (LPF3) and take the square root of the result ⋅ ⋅ ω With V t then ( ) V 2 sin ...
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... Micro-controller with a specific Ampere/LSB constant for each phase - see Calibration of a 3-phase meter based on the ADE7754. Due to gain mismatches between phases, the calibration of the Ampere/ LSB constant has to be done for each phase separately. One point calibration is sufficient for this calibration ...
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... P is referred to as the Active or Real Power. Note that the active power is equal to the DC component of the instanta- neous power signal p(t) in Equation 5 , i.e., VI. This is the relationship used to calculate active power in the ADE7754 for each phase. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals in each phase ...
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... Active Power Gain and Watt Gain registers. These can be used to calibrate the Active Power (or Energy) calculation in the ADE7754 for each phase and also the Total Active Energy -see Total Active Power calculation. HPF ...
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... Different gain calibration parameters are offered in the ADE7754 to cover the calibration of the meter in different configurations. It should be noticed that in Mode 0, APGAIN and WGAIN registers have the same effect on the end result. In this case, APGAIN registers should be set at their default value and the gain adjustment should be done with the WGAIN registers ...
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... Conversely if the power is negative the energy register would under flow to full scale positive (7F,FFFFh) and continue decreasing in value. By using the Interrupt Enable register, the ADE7754 can be configured to issue an interrupt (IRQ) when the Active 0 Energy register is half full (positive or negative). TOTAL ACTIVE POWER ARE ...
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... CFDEN=00h) with full scale AC signals on the three phases i.e. current channel and voltage channel is approximately 96kHz. The ADE7754 incorporates two registers to set the frequency of CF (CFNUM[11:0] and CFDEN[11:0]). These are unsigned 12-bit registers which can be used to adjust the frequency wide range of values. These Frequency ...
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... Zero-crossing Detection paragraph. The number of half line cycles is specified in the LINCYC register. LINCYC is an unsigned 16-bit register. The ADE7754 can accumulate Active Power for up to 65535 combined half cycles. Because the Active Power is integrated on an integer number of line cycles, the sinusoidal compo- nent is reduced to zero ...
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... E(t) VInT (16) The total active power calculated by the ADE7754 in the Line accumulation mode depends on the configuration of the WATMOD bits in the WATMode register. Each term of the formula can be disabled or enabled by the LWATSEL bits of the WATMode register. The different configurations are described in Table III. ...
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... IRQ output will also go active low. Thus the IRQ line can also be used to signal the end of a calibration. As explained in the Reactive Power paragraph, the purpose of the reactive Energy calculation in the ADE7754 is not to give an accurate measurement of this value but to to provide the sign of the the reactive energy. The ADE7754 provides an accurate measurement of the Apparent Energy ...
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... Apparent Power Gain register content is equal to 800h and the maximum range is given by writing 7FFh to the Apparent Power Gain register. This can be used to calibrate the Apparent Power (or Energy) calculation in the ADE7754 for each phase and also the Total Apparent Energy -see Total Apparent Power calculation. ...
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... Wye 0 Table V - Meter form configuration Different gain calibration parameters are offered in the ADE7754 to cover the calibration of the meter in different configurations. These registers, APGAIN, VGAIN and VAGAIN, have different purposes in the signal processing of the ADE7754. APGAIN registers affect the Apparent power calculation but should be used only for Active Power calibration ...
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... Figure 36. By using the Interrupt Enable register, the ADE7754 can be configured to issue an interrupt (IRQ) when the Apparent Energy register is half full (positive or negative). Integration times under steady load As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.2µ ...
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... PRELIMINARY TECHNICAL DATA ADE7754 The total apparent power calculated by the ADE7754 in the Line accumulation mode depends on the configuration of the VAMOD bits in the VAMode register. Each term of the formula can be disabled or enabled by the LVASEL bits of the VAMode register. The different configurations are de- scribed in Table VI ...
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... The CS logic input may be tied low if the ADE7754 is the only device on the serial bus. However with CS tied low, all initiated data transfer opera- tions must be fully completed, i.e., the LSB of each register ...
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... The six LSBs of this byte contain the address of the register which read. The ADE7754 starts shifting out of the register data on the next rising edge of SCLK – see Figure 44. At this point the DOUT logic output switches from high impedance state and starts driving the data bus ...
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... ADE7754, the corresponding flag in the Interrupt Status register is set to a logic one - see ADE7754 Interrupt Status register. If the mask bit for this interrupt in the Interrupt Mask register is logic one, then the IRQ logic output goes active low. The flag bits in the Interrupt Status register are set irrespective of the state of the mask bits ...
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... Interface section of this data sheet. Communications Register The Communications register is an eight bit, write-only register which controls the serial data transfer between the ADE7754 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed ...
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... IRQ Mask register. It determines if an interrupt event will gener- ate an active-low output at IRQ pin - see Table XVI. 0 IRQ Status register. This register contains information regarding the source of ADE7754 interrupts - see Table XVII. 0 Same as the STATUS register. Except that its contents are reset to zero (all flags cleared) after a read operation. ...
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... PRELIMINARY TECHNICAL DATA ADE7754 Address [A5:A0] Name R/W* Length 12h R/W 16 13h LINCYC R/W 16 14h SAGCYC R/W 8 15h R/W 8 16h VPEAK R/W 8 17h IPEAK R/W 8 18h GAIN R/W 8 19h R/W 12 1Ah R/W 12 1Bh R/W 12 1Ch AVAG R/W 12 1Dh BVAG R/W 12 1Eh CVAG R/W 12 1Fh ...
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... LSB - see Voltage RMS Gain Adjust 0 Phase B voltage RMS gain 0 Phase C voltage RMS gain Reserved Check sum register. The content of this register represents the sum of all ones of the latest register read from the SPI port. 1 Version of the Die –37– ADE7754 ...
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... PRELIMINARY TECHNICAL DATA ADE7754 Operational Mode Register (0Ah) The general configuration of the ADE7754 is defined by writing to the OPMODE register. Table IX below summarizes the functionality of each bit in the OPMODE register . Bit Bit Default Location Mnemonic Value Description 0 DISHPF 0 The HPF (High Pass Filter) in all current channel inputs are disabled when this bit is set. ...
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... PRELIMINARY TECHNICAL DATA Gain Register (18h) The Gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing to the GAIN register. Table X below summarizes the functionality of each bit in the GAIN register . Bit Bit Default Location Mnemonic ...
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... LVARSEL 0 This bit is used to enable the accumulation of the Line VAR energy into the LAENERGY register and of the Line Active Energy into the LVAENERGY register. measurements made by the ADE7754 are defined by writing to the MMODE Table XII MMODE Register bit 0 Source 0 Phase A ...
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... PRELIMINARY TECHNICAL DATA Watt Mode Register (0Dh) The phases involved in the Active Energy measurement of the ADE7754 are defined by writing to the WATMODE register. Table XIV below summarizes the functionality of each bit in the WATMODE register . Bit Bit Default Location Mnemonic Value Description 0 These bits are used to select separately each part of the formula, depending on the Line Active Energy measurement method ...
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... Interrupt Mask Register (0Fh) When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the mask bit for this event is logic one in this register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. The following describes the function of each bit in the Interrupt Mask Register ...
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... The Interrupt Status Register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7754, the corresponding flag in the Interrupt Status Register is set logic high. The IRQ pin will go active low if the corresponding bit in the Interrupt Mask register is set logic high. When the MCU services the interrupt, it must first carry out a read from the Interrupt Status Register to determine the source of the interrupt ...
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... PRELIMINARY TECHNICAL DATA ADE7754 PIN 1 0.0118 (0.30) 0.0040 (0.10) OUTLINE DIMENSIONS shown in inches and (mm) 24-LEAD SOIC (RW-24) 0.6141 (15.60) 0.5985 (15.20 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 8 0.0500 0.0192 (0.49) SEATING 0 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0091 (0.23) BSC –44– 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) REV. PrG 01/03 ...