74HCT9046AN Philips, 74HCT9046AN Datasheet - Page 7

• Manufacturer Part Number: 74HCT9046AN
• Description: PLL with bandgap controlled VCO
• Manufacturer: Philips

Philips Semiconductors
Phase comparators
The signal input (SIG
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
P
This circuit is an EXCLUSIVE-OR
network. The signal and comparator
input frequencies (f
50% duty factor to obtain the
maximum locking range. The transfer
characteristic of PC1, assuming
ripple (f
where:
The phase comparator gain is:
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
phase differences of signals (SIG
and the comparator input (COMP
as shown in Fig.6. The average of
V
there is no signal or noise at SIG
and with this input the VCO oscillates
at the centre frequency (f
waveforms for the PC1 loop locked at
f
shows the actual waveforms across
the VCO capacitor at pins 6 and 7
(V
between these ramps and the
VCO
1999 Jan 11
V
K
c
HASE COMPARATOR
DEMOUT
DEMOUT
p
are shown in Fig.7. This figure also
V
at pin 10.
V
DEMOUT
C1A
PLL with bandgap controlled VCO
DEMOUT
DEMOUT
=
OUT
and V
V
---------- - V r
r
CC
= 2f
voltage.
), is the resultant of the
is equal to
=
is the demodulator output
= V
C1B
i
V
---------- -
) is suppressed, is:
CC
PC1OUT
) to show the relation
i
) must have a
1 (PC1)
SIGIN
1
IN
2
(via low-pass).
V
) can be
CC
c
–
). Typical
when
COMPIN
IN
IN
IN
)
)
The frequency capture range (2f
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2f
as the frequency range of the input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration remains
locked even with very noisy input
signals. Typical behaviour of this type
of phase comparator is that it may
lock to input frequencies close to the
harmonics of the VCO centre
frequency.
P
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIG
PC2 comprises two D-type flip-flops,
control gating and a 3-state output
stage with sink and source transistors
acting as current sources, henceforth
called charge pump output of PC2.
The circuit functions as an up-down
counter (Fig.5) where SIG
an up-count and COMP
count. The current switch charge
pump output allows a virtually ideal
performance of PC2, due to appliance
of some pulse overlap of the up and
down signals. See Fig.8a.
HASE COMPARATOR
IN
and COMP
IN
7
are not important.
2 (PC2)
IN
L
) is defined
IN
a down
causes
c
) is
74HCT9046A
Product specification