74HCT9046AN Philips, 74HCT9046AN Datasheet - Page 33

• Manufacturer Part Number: 74HCT9046AN
• Description: PLL with bandgap controlled VCO
• Manufacturer: Philips

Philips Semiconductors
PLL design example
The frequency synthesizer used in
the design example shown in Fig.34
has the following parameters:
The open loop gain is:
H (s)
and the closed loop:
where:
The programmable counter ratio K
can be found as follows:
The VCO is set by the values of R1,
R2 and C1; R2 = 10 k (adjustable).
The values can be determined using
the information in Table 3.
With f
this gives the following values
(V
The VCO gain is:
1999 Jan 11
N
K
------ -
N
1 MHz
---------------- - 2
v
min
max
u
2.8
Output frequency: 2 MHz to 3 MHz.
Frequency steps: 100 kHz.
Settling time: 1 ms.
Overshoot: <20%.
K
K
K
K
CC
R1 = 30 k .
R2 = 30 k .
C1 = 100 pF.
i
PLL with bandgap controlled VCO
p
f
o
n
=
=
= low-pass filter transfer gain
= phase comparator gain
= K
=
= 5.0 V):
c
=
--------------------------------------------- -
1
=
----------------------------------------------------- -
1
= 2.5 MHz and f
G (s) = K
V
K
+
f
----------- -
n
f
v
f
----------- -
f
OUT
CC
step
/s VCO gain
OUT
step
p
divider ratio.
K
2f
p
–
L
K
1.1
=
2.24 10
=
f
K
p
2
--------------------- -
100 kHz
f
--------------------- -
100 kHz
2 MHz
K
3 MHz
–
o
K
K
1.1
o
f
K
L
6
K
n
K
= 500 kHz
r s V
=
o
n
=
=
20
30
K
n
n
The gain of the phase comparator
PC2 is:
Using PC2 with the passive filter as
shown in Fig.34 results in a high gain
loop with the same performance as a
loop with an active filter. Hence loop
filter equations as for a high gain loop
should be used. The current source
output of PC2 can be simulated then
with a fictive filter resistance:
The transfer functions of the filter is
given by:
Where:
The characteristic equation is:
This results in:
or:
This can be written as:
with the natural frequency
as:
damping value given as:
In Fig.35 the output frequency
response to a step of input frequency
is shown.
The overshoot and settling time
percentages are now used to
determine
K
K
1
1
s
s
R3'
2
2
p
f
+
+
=
+
+
1
2
=
=
K
K
= R3'
= R4
sK
2
0.5
=
p
p
n
1
----------------- -
------------
4
R
------ -
17
=
+
s
p
1
----------------- -
5
K
K
b
n
s
+
s
2
s
f
v
K
2
s
K
------------------------------- -
2
+
C2.
n
1
=
C2.
n
p
. From Fig.35 it can be
K
2
---- -
0.4V r
o
2
1
K
----- - K
n
K
+
n
s
33
1
v
v
K
K
2
n
p
n
=
K
K
=
v
n
0
K
0
and the
n
n
1
defined
=
0
seen that the damping ratio = 0.707
will produce an overshoot of less than
20% and settle to within 5% at
The required settling time is 1 ms.
This results in:
Rewriting the equation for natural
frequency results in:
The maximum overshoot occurs at
N
When C2 = 470 nF, it follows:
Hence the current source bias
resistance R
With = 0.707 (0.5
follows:
For extra ripple suppression a
capacitor C3 can be connected in
parallel with R4, with an extra
For stability reasons
C3 = 39 nF.
R4
R3'
3
0.1
1
1
2
max
n
= R4
=
=
=
=
=
=
2
= 30; hence K
K
------------------------------- -
0.4 2.24 10
----------------------------------------- -
--------------------------- -
0.5 5000
, hence C3
5
-- -
t
------- -
C2
p
------- -
C2
5000
0.707
2
=
1
C3.
K
=
-------------- -
0.001
=
n
v
b
2
5
--------------------------- -
470 10
= 17
74HCT9046A
2
--------------------------- -
470 10
0.00028
K
0.0012
Product specification
30
n
=
=
n
0.1C2, or
0.00028
5 10
6
=
2550 = 43 k .
3
2
–
=
–
1
9
should be
9
30
0.0012
=
=
:
3
n
600
r s
2550
) it
n
t = 5.