AD7824 Analog Devices, AD7824 Datasheet - Page 9

• Manufacturer Part Number: AD7824
• Description: LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs
• Manufacturer: Analog Devices

MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors which have a WAIT
state facility, whereby a READ instruction cycle can be extended to
accommodate slow memory devices. A READ operation brings
CS and RD low which starts a conversion. The analog multiplexer
address inputs must remain valid while CS and RD are low.
The data bus (DB7–DB0) remains in the three-state condition
until conversion is complete. There are two converter status
outputs on the AD7824/AD7828, interrupt (INT) and ready
(RDY) which can be used to drive the microprocessor READY/
WAIT input. The RDY is an open drain output (no internal
pull-up device) which goes low on the falling edge of CS and
goes high impedance at the end of conversion, when the 8-bit
conversion result appears on the data outputs. If the RDY status
is not required, then the external pull-up resistor can be omitted
and the RDY output tied to GND. The INT goes low when
conversion is complete and returns high on the rising edge of
CS or RD.
MODE 1
Mode 1 operation is designed for applications where the micro-
processor is not forced into a WAIT state. A READ operation
takes CS and RD low which triggers a conversion (see Figure
15). The multiplexer address inputs are latched on the rising
edge of RD. Data from the previous conversion is read from the
three-state data outputs (DB7–DB0). This data may be disre-
garded if not required. Note, the RDY output (open drain out-
put) does not provide any status information in this mode and
must be connected to GND. At the end of conversion INT
goes low. A second READ operation is required to access the
new conversion result. This READ operation latches a new
address into the multiplexer inputs and starts another conversion.
INT returns high at the end of the second READ operation,
when CS or RD returns high. A delay of 2.5 µs must be allowed
between READ operations.
AD7824/AD7828