AD7824 Analog Devices, AD7824 Datasheet - Page 10

• Manufacturer Part Number: AD7824
• Description: LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs
• Manufacturer: Analog Devices

AD7824/AD7828
MICROPROCESSOR INTERFACING
The AD7824/AD7828 is designed to interface to microproces-
sors as Read Only Memory (ROM). Analog channel selection,
conversion start and data read operations are controlled by CS,
RD and the channel address inputs. These signals are common
to all memory peripheral devices.
Z80 MICROPROCESSOR
Figure 16 shows a typical AD7824/AD7828–Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow-
ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the con-
version result.
At the beginning of the instruction cycle when the ADC ad-
dress is selected, RDY asserts the WAIT input, so that the Z80
is forced into a WAIT state. At the end of conversion RDY
returns high and the conversion result is placed in the B register
of the microprocessor.
Address
C000
C001
C002
C003
C004
C005
C006
C007
Table II. Address Channel Selection
LD B, (C000)
AD7824
Channel
1
2
3
4
AD7828
Channel
1
2
3
4
5
6
7
8
MC68000 MICROPROCESSOR
Figure 17 shows a MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
to any of the addresses in Table II starts a conversion and reads
the conversion result.
Once conversion has begun, the MC68000 inserts WAIT states,
until INT goes low asserting DTACK at the end of conversion.
The microprocessor then places the conversion results in the
D0 register.
TMS32010 MICROCOMPUTER
A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no µP WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5 µs must be allowed
between conversions.
IN, A PA (PA = PORT ADDRESS)
MOVE•B $C000,D0