SC16C652BIBS PHILIPS [NXP Semiconductors], SC16C652BIBS Datasheet - Page 19

• Manufacturer Part Number: SC16C652BIBS
• Description: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14452
Product data
7.3.2 FIFO mode
Table 11:
Bit
7:6
5:4
3
2
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FIFO Control Register bits description
Rev. 03 — 10 December 2004
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C652B will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level.
Refer to
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C652B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C652B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C652B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C652B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
XMIT FIFO reset.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table
13.
Table
12.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C652B
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