SC16C652BIBS PHILIPS [NXP Semiconductors], SC16C652BIBS Datasheet - Page 16

• Manufacturer Part Number: SC16C652BIBS
• Description: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14452
Product data
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the
SC16C652B and receive FIFO by reading the RHR register. The receive section
provides a mechanism to prevent false starts. On the falling edge of a start or false
start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After
7-
time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assembling a false character. Receiver
status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 10:
Bit
7
6
5
4
3
1
2
clocks, the start bit time should be shifted to the center of the start bit. At this
Interrupt Enable Register bits description
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
Rev. 03 — 10 December 2004
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Description
CTS interrupt.
RTS interrupt.
Xoff interrupt.
Sleep mode.
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0:3].
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C652B issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C652B issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff
interrupt.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode.
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C652B
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