LTC1668 LINER [Linear Technology], LTC1668 Datasheet - Page 7

• Manufacturer Part Number: LTC1668
• Description: 16-Bit, 50Msps DAC
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Substituting the values found earlier for I
I
From these equations some of the advantages of differen-
tial mode operation can be seen. First, any common mode
noise or error on I
signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I
I
midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.
Note that the term (R
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R
temperature tracking of R
the absolute tempco of R
nonlinearity. As the DAC output changes from 0mA to
10mA the R
very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.
Analog Outputs
The LTC1668 has two complementary current outputs,
I
impedance of I
typically 1.1k to LADCOM. (See the Equivalent Analog
Output Circuit, Figure 1.) The LADCOM pin is the com-
mon connection for the internal DAC attenuator ladder. It
usually is tied to analog ground, but more generally it
should connect to the same potential as the lead resistors
on I
current to V
current that flows from I
R
OUTFS
OUT B
OUT A
LOAD
IOUT A
V
(R
OUT A
DIFF
LOAD
:
, such as reference or I
and I
to R
and R
= {2 • DAC Code – 65535)/65536} • 8 •
and I
/R
SET
OUT B
LOAD
SS
SET
, and the Gain Error tempco is affected by the
IOUT B
OUT B
of approximately 0.32 • (I
) • (V
OUT A
(see DAC Transfer Function). The output
resistor will heat up slightly, and even a
OUT A
U
. The LADCOM pin carries a constant
REF
resistors.
and I
and I
LOAD
)
U
LOAD
OUT A
OUT B
OUT B
LOAD
/R
SET
OUTFS
with R
(R
is cancelled. Second, the
and I
is very critical for DC
) appears in both the
W
IOUT A
noise, cancel near
SET
OUT B
OUT A
OUTFS
. Note also that
and R
through the
, I
), plus any
U
OUT A
OUT B
IOUT B
and
and
) is
(7)
The specified output compliance voltage range is 1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below – 1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than 0.5V
I
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
The LTC1668 is specified to operate with full-scale output
current, I
This can be useful to reduce power dissipation or to adjust
full-scale value. However, that the LTC1668 DC and AC
accuracy is specified only at I
AC accuracy will fall off significantly at lower I
At I
bit to 13-bit level, compared to 16-bit to 15-bit typical
accuracy at 10mA I
OUT B
LTC1668
OUTFS
due to nonlinear capacitance and other large-signal
= 1mA, INL and DNL typically degrade to the 14-
OUTFS
Figure 1. Equivalent Analog Output Circuit
, from the nominal 10mA down to 1mA.
OUT A
OUTFS
R
. Increasing I
into the virtual ground of an
IOUT B
1.1k
5pF
OUTFS
R
1.1k
IOUT A
= 10mA, and DC and
OUTFS
LADCOM
5pF
I
I
P-P
OUT A
OUT B
LTC1668
V
SS
from 1mA, the
on I
OUTFS
18
20
19
23
1668 F01
OUT A
values.
52.3
52.3
– 5V
7
and