LTC1668 LINER [Linear Technology], LTC1668 Datasheet - Page 10

• Manufacturer Part Number: LTC1668
• Description: 16-Bit, 50Msps DAC
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1668
cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled imped-
ance and should be well terminated near the LTC1668.
Printed Circuit Board Layout Considerations—
Grounding, Bypassing and Output Signal Routing
The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
necessity. Figures 5 to 9 are the printed circuit board layers
for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1 F or larger with low ESR.
10
U
U
W
U
Bypass capacitors are required on V
and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1 F bypass capacitor. It should be bypassed
to V
should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The I
I
matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.
Suggested Evaluation Circuit
Figure 4 is the schematic and Figures 5 to 9 are the circuit
board layouts for a suggested evaluation circuit, DC245A.
The circuit can be programmed with component selection
and jumpers for a variety of differentially coupled trans-
former output and differential and single-ended resistor
loaded output configurations.
OUT B
SS
traces should be close together, short, and well
along with COMP1. The AGND and DGND pins
SS
, V
DD
and REFOUT,
OUT A
and