msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 18

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
INTA
INTERRUPT ACKNOWLEDGE: Output
ALE
ADDRESS LATCH ENABLE: Output
DT/R
DATA TRANSMIT/RECEIVE: Output
DEN
DATA ENABLE: Output
HOLD
HOLD REQUEST: Input
HLDA
HOLD ACKNOWLEDGE: Output
This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low.
This line is used for latching the address into the MSM82C12 address latch. It is a positive
pulse and its trailing edge is used to strobe the address. This line is never floated.
This line is used to control the output enable of the bus transceiver.
When this line is high, the CPU transmits data, and when it is low. the CPU receives data.
This line is high impedance during hold acknowledge.
This line is used to control the output enable of the bus transceiver.
This line is active low. This line is high impedance during hold acknowledge.
This line is used for Bus Request from other devices.
This line is active high.
This line is used for Bus Grant other devices.
This line is active high.
MSM80C86A-10RS/GS/JS
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