msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 13

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Maximum Mode (continued)
MSM82C88-2 Outputs
Software Halt
(DEN = V
AMWC, IOWC, AIOWC, INTA = V
See NOTES 5, 6
Notes: 1. All signals switch between V
MSM82C88-2 Outputs
CLK (MSM82C84A-2 Output)
Write Cycle
INTA Cycle
OL
; RD, MRDC, IORC, MWTC,
See NOTES 5, 6
2. RDY is sampled near the end of T2, T3, T
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/
5. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.
6. The issuance of the MSM 82C88-2 command and control signals (MRDC,
7. All timing measurements are made at 1.5 V unless otherwise noted.
8. Status inactive in state just prior to T4
S
2
states are to be inserted.
DATA BUS is floating during both INTA cycles. Control for pointer address
is shown for second INTA cycle.
MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high MSM82C88-2 CEN.
, S
See NOTE 3, 4
1
AMWC or AIOWC
AD
, S
MWTC or IOWC
0
15
(Except Halt)
- AD
AD
AD
S
2
15
15
, S
0
OH
PDEN
- AD
- AD
MCE/
DT/R
INTA
1
DEN
DEN
, S
)
V
V
IH
IL
0
0
0
t
t
t
CLAV
SVMCH
CLMCH
t
Float
CLAV
t
CHSV
t
OH
t
t
T
CVNX
CVNV
CLML
t
1
t
CLAX
CLAZ
Invalid Address
and V
Float
t
CHDTL
OL
t
CLML
t
T
CLDV
2
unless otherwise specified.
W
Float
 
to determine if T
t
CVNV
MSM80C86A-10RS/GS/JS
t
t
CLML
Data
t
t
t
CVNX
CLSH
CLMH
DVCL
Pointer
T
3
T
w
t
t
CHDX
CVNX
(See
NOTE 8)
t
CLMH
W
T
t
t
4
CLMH
CLDX
machines
Float
13/37
t
CHDTH