com81c17 Standard Microsystems Corp., com81c17 Datasheet - Page 10

• Manufacturer Part Number: com81c17
• Description: Twenty Pin Uart Tpuart Corporation
• Manufacturer: Standard Microsystems Corp.

BIT
BIT
0
1
2
3
4
5
6
7
7
RX BUFFER FULL - This signals the processor that a completed character is present in
the Receive Buffer Register for transfer to the processor. This bit is set when a character
has been loaded from the receive deserialization logic to the Receive Buffer Register.
This bit is cleared by:
Not used (test mode bit, must be zero).
CP2 – This bit controls the nCP2 output pin.
compliment of the register data. When the CP2 bit is set, the nCP2 pin is forced low.
When CP2 is RTS, a 1 to 0 transition of the CP2 bit will cause the nCP2 pin to go high
one TXc time after the last serial bit has been transmitted.
RX ENABLE – This bit when reset will disable the setting of the RX BUFFER FULL bit
in the Status Register which informs the processor of the availability of a received
character in the Receive Buffer Register. The error bits in the Status Register will be
cleared and will remain cleared when RX is disabled.
RX RESET – This will reset the receiver block only.
TX RESET – This will reset the transmitter block only.
TX ENABLE – Data transmission cannot take place by the TPUART unless this bit is
set.
previously written data has been transmitted.
RESET ERRORS – This bit when set will reset the parity, overrun, and framing error
bits in the Status Register. No latch is provided in the Control Register for saving this
bit; therefore there is no need to clear it (error reset = d6.RS.nWR).
INTERNAL RESET – This bit enables the resetting of the internal circuitry and initializes
access to address 0 to be sequential.
A)
B)
C)
Table 5 – COM81C17 CONTROL REGISTER DESCRIPTION (BITS 0-7)
When this bit is reset (disable), transmission will be disabled only after the
Reading the Receive Buffer Register
Asserting the RECEIVER RESET bit in the Control Register
Asserting internal reset
DESCRIPTION
DESCRIPTION
10
Data at the output is the logical