hd61603r ETC-unknow, hd61603r Datasheet - Page 5

• Manufacturer Part Number: hd61603r
• Description: Segment Type Lcd Driver
• Manufacturer: ETC-unknow

HD61602/HD61603
Terminal Functions
HD61602 Terminal Functions
Terminal
Name
VDD
READY
&6
:(
5(
SB
D0–D7
VSS
VREF1
VREF2
VC1, VC2
V1, V2, V3
COM0–COM3 4
SEG0–SEG50 51
SYNC
OSC1
OSC2
Note: Logic polarity is positive. 1 = high = active.
1234
No. of
Lines
1
1
1
1
1
8
1
1
1
3
1
2
1
2
Output
Input/Output
Power supply
NMOS open
drain output
Input
Input
Input
Input
Input
Power supply
Output
Input
Output
Output (Input) External C
Output
Input
Input
Output
Connected to Function
MCU
MCU
MCU
MCU
MCU
MCU
External R
External R
External C
LCD
LCD
MCU
External R
While data is being set in the display data RAM
and mode setting latch in the LSI after data
transfer, low is output from the READY terminal
to inhibit the next data input.
There are two modes: one in which low is output
only when both of
other in which low is output regardless of
5(
Chip select input. Data can be written only when
this terminal is low.
Write enable input. Input data of D0 to D7 is
latched at the rising edge of
Resets the input data byte counter. After both
&6
as the 1st byte data.
High level input stops LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
Data input terminal for 8-bit
Reference voltage output. Generates LCD
driving voltage.
Divides the reference voltage of VREF1 with
external R to determine LCD driving voltage.
VREF2
Connection terminals for boosting C of LCD
driving voltage generator. An external C is
connected between VC1 and VC2.
LCD driving voltage outputs. An external C is
connected to each terminal.
LCD common (backplate) driving output.
LCD segment driving output.
Synchronous input for 2 or more chips
applications. LCD driver timing circuit is reset by
high input. LCD is off.
oscillation. An external clock (100 kHz) can be
input to OSC1.
Positive power supply.
Negative power supply.
Attach external R to these terminals for
.
and
5(
V1.
are low, the first data is recognized
&6
and
5(
:(
2-byte data.
are low, and the
.
&6
and