thc63lvd104c THine Electronics,Inc., thc63lvd104c Datasheet

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thc63lvd104c

Manufacturer Part Number
thc63lvd104c
Description
112mhz 30bits Color Lvds Receiver
Manufacturer
THine Electronics,Inc.
Datasheet

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Copyright©2009 THine Electronics, Inc.
THC63LVD104C_Rev.1.00_E
General Description
The THC63LVD104C receiver is designed to support
pixel data transmission between Host and Flat Panel
Display from NTSC up to SXGA resolutions. The
THC63LVD104C converts the LVDS data streams back
into 35bits of CMOS/TTL data with the choice of the
rising edge or falling edge clock for the convenience
with a variety of LCD panel controllers.At a transmit
clock frequency of 112MHz, 30bits of RGB data and
5 b i t s o f t i m i n g a n d c o n t r o l d a t a ( H S Y N C ,
VSYNC,DE,CNTL1,CNTL2) are transmitted at an
effective rate of 784Mbps per LVDS channel.Using a
112MHz clock, the data throughput is 490Mbytes per
second.
Block Diagram
LVDS INPUT
CMOS/TTL INPUT
(8 to 112MHz)
RCLK+/-
TEST
RA+/-
RC+/-
RD+/-
RB+/-
RE+/-
R/F
OE
PD
112MHz 30Bits COLOR LVDS Receiver
THC63LVD104C
PLL
Features
1/13
Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA
PLL requires no external components
50% output clock duty cycle
TTL clock edge programmable
Power down mode
Low power single 3.3V CMOS design
64pin TQFP
Backward compatible with THC63LVDF64x
(18bits) / F84x(24bits)
Pin compatible with THC63LVD104A
Fail-safe for Open LVDS Input
7
7
7
7
7
CMOS/TTL OUTPUT
RA6-RA0
RB6-RB0
RC6-RC0
RD6-RD0
RE6-RE0
CLKOUT
THine Electronics, Inc.

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thc63lvd104c Summary of contents

Page 1

... The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back into 35bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers ...

Page 2

... THC63LVD104C_Rev.1.00_E Pin Out RA- 49 RA+ 50 RB- 51 RB+ 52 LVCC 53 RC- 54 RC+ 55 RCLK- 56 RCLK+ 57 LGND 58 RD- 59 RD+ 60 RE- 61 RE+ 62 PGND 63 PVCC 64 Copyright©2009 THine Electronics, Inc 2/13 THine Electronics, Inc. THine RB6 CLKOUT GND RC0 ...

Page 3

... THC63LVD104C_Rev.1.00_E Pin Description Pin Name Pin # RA+, RA- 50, 49 RB+, RB- 52, 51 RC+, RC- 55, 54 RD+, RD- 60, 59 RE+,RE- 62, 61 RCLK+, RCLK- 57, 56 RA6 ~ RA0 40,41,42,43,45,46,47 RB6 ~ RB0 32,33,34,35,36,38,39 RC6 ~ RC0 22,24,25,26,27,28,29 RD6 ~ RD0 14,15,17,18,19,20,21 RE6 ~ RE0 6,7,8,10,11,12,13 TEST R/F 5 VCC 9,23,37,48 CLKOUT 31 GND 1,16,30,44 LVCC 53 LGND 58 PVCC 64 PGND 63 PD ...

Page 4

... THC63LVD104C_Rev.1.00_E Absolute Maximum Ratings Supply Voltage (V =VCC=LVCC=PVCC) CC CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 Electrical Characteristics CMOS/TTL DC Specifications Symbol Parameter V High Level Input Voltage ...

Page 5

... THC63LVD104C_Rev.1.00_E Supply Current Symbol Parameter Receiver Supply I Current RCCW (LVDS Full Toggle) Receiver Power Down I RCCS Supply Current *The trade-off between the output load and the ambient temperature exists so that the junction temperature does not °C exceed 125 . LVDS Full Toggle Pattern ...

Page 6

... THC63LVD104C_Rev.1.00_E Output load limitation The output load is limited so that the junction temperature does not exceed 125 25.0 20.0 15.0 10.0 5.0 0.0 8 Copyright©2009 THine Electronics, Inc. Ta=70℃ Ta=85℃ Frequency[MHz] 6/13 THine ° 108 THine Electronics, Inc. ...

Page 7

... THC63LVD104C_Rev.1.00_E Switching Characteristics Symbol Parameter t CLKOUT Period RCP t CLKOUT High Time RCH t CLKOUT Low Time RCL t TTL Data Setup to CLKOUT RS t TTL Data Hold from CLKOUT RH t TTL Low to High Transition Time TLH t TTL High to Low Transition Time THL Receiver Skew ...

Page 8

... THC63LVD104C_Rev.1.00_E AC Timing Diagrams TTL Outputs TTL Output C TTL Output Load Copyright©2009 THine Electronics, Inc. 80% =8pF L 20% t TLH 8/13 THine 80% 20% t THL THine Electronics, Inc. ...

Page 9

... THC63LVD104C_Rev.1.00_E AC Timing Diagrams TTL Outputs CLKOUT VCC/2 Rxn x = A,B,C,D 0,1,2,3,4,5,6 Phase Lock Loop Set Time VCC RCLK+/- PD CLKOUT Copyright©2009 THine Electronics, Inc. t RCH VCC/2 t RCP t RS VCC/2 3.0V 2.0V 9/13 t RCL R VCC/2 R VCC/2 t RPLL 2.0V THine Electronics, Inc. ...

Page 10

... THC63LVD104C_Rev.1.00_E AC Timing Diagrams LVDS Inputs diff RCLK+ (Differential) RA+/- RA3’ RA2’ RA1’ RA0’ RB+/- RB3’ RB2’ RB1’ RB0’ RC+/- RC3’ RC2’ RC1’ RC0’ RD+/- RD3’ RD2’ RD1’ RD0’ ...

Page 11

... Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 3)GND Connection Connect the each GND of the PCB which LVDS-Tx and THC63LVD104C on it better for EMI reduction to place GND cable as close to LVDS cable as possible. 4)Multi Drop Connection Multi drop connection is not recommended ...

Page 12

... THC63LVD104C_Rev.1.00_E Package INDEX Δ PIN No.1 16 Copyright©2009 THine Electronics, Inc 12/ UNITS: mm THine Electronics, Inc. ...

Page 13

... THC63LVD104C_Rev.1.00_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material ...

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