ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 23

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

23
Status Registers
Register 27 ADDR 11011 (bin) 1B (hex) All bits are Read Only
Bit
STATUS REGISTERS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPLINKSTATUS
FOBADFREQ
FOFORCELO
TPFORCELO
TPBADFREQ
FEFDETECT
DATACTOF
DATAFTOC
ANCOMPL
Name
NOSEED
FOIN100
TPIN100
FOIN10
TPIN10
FLNP
FLP
Description
This bit set high when the fiber optic input PLL follows the local oscillator
This bit set high when there is a large difference between the frequency of the reference
clock and the frequency of the VCO of the fiber optic input PLL. The low frequency
threshold is between 121 and 123MHz, and the high frequency threshold is between 127
and 129MHz. This indicator is disabled when "FSENSEDIS" bit <28.3> is 1 or when the
filter of the PLL is being reset.
This bit set high when the Far End Fault (FEF) pattern is detected at the fiber optic input
interface
This bit set high when the twisted pair input PLL follows the local oscillator
This bit set high when there is a large difference between the frequency of the reference
clock and the frequency of the VCO of the twisted pair input PLL. The low frequency
threshold is between 121 and 123MHz, and the high frequency threshold is between 127
and 129MHz. This indicator is disabled when "FSENSEDIS" bit <28.3> is 1 or when the
filter of the PLL is being reset.
This bit set high when the descrambler is enabled and the seed is not updated for 1.3ms
to 2ms. This bit set low when the seed is updated. The high value is latched until it’s
read. Default is 0
This bit set high when the twisted pair link is up. This bit is latched low until read. It only
applies to NON-TRANSPARENT Mode. It is always low in TRANSPARENT Mode
Auto-Negotiation Complete. This bit set high indicates that the Auto-Negotiation process
on the twisted pair link is completed. It only applies to NON-TRANSPARENT Mode. It is
always low in TRANSPARENT Mode
This bit set high indicates that 100Mbps signal is being detected at the twisted pair input
interface
This bit set high indicates that 10Mbps signal is being detected at the twisted pair input
interface
This bit set high indicates that a data packet has been detected at the twisted pair input.
This bit is latched high until it’s read. This bit is always low if both TPIN10 and TPIN100
are low
This bit set high, when FLP Bursts are detected at the twisted pair input interface. It is
also set high when FLNP Bursts are detected at the twisted pair interface when PECL
mode is selected for it
This bit set high when 100BASE-FX or 100BASE-SX signal is being detected at the fiber
optic input interface
This bit set high when 10BASE-FL signal is being detected at the fiber optic input
interface
This bit set high when a data packet has been detected at the fiber optic input. This bit is
latched high until it’s read. This bit is always low if both FOIN10 and FOIN100 are off
This bit set high when FLNP Bursts are detected at the fiber optic input interface
January 2004
Final Datasheet
DS6652-F-02
ML6652