ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 14

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

14
DEVICE CONFIGURATION
Configuring the ML6652 Media Converter is
accomplished through input configuration pins or bits in
management control register 30. Configuration pins
AD4LIW, AD32 and AD10 determine the PHY address
used with the serial management interface consisting of
MDIO (pin 16) and MDC (pin 17). The setting of any R/W
bit in the control management registers can be modified
by writing data to the register through the serial
management interface. The control management registers
27, 28, 30, and 31 always indicate the current operating
mode of the ML6652.
The PHY address settings defined by AD4LIW (pin 4),
AD32 (pin 5), and AD10 (pin 6) are latched and must
remain stable during any serial management interface
read or write operation. The PHY address pins each have
four (4) distinct input levels and together encode the
required five (5) bit PHY addresses. Nominal values of
VCC and 0V are obtained with directions to VCCD or
GNDD. Nominal values of 2/3 VCC and 1/3 VCC must be
developed with external resistor dividers.
Input pins SPEED (pin 27) and DUPLEX (pin 25) are three
level inputs having internal 80kΩ resistors connected to
both VCC and Ground. Nominal input voltage levels are
VCC, VCC/2, when input is left floating, and Ground. The
state of configuration pins DUPLEX, SPEED, PECLTP (pin
7) PECLQU (pin 8), and AD4LIW (pin 4) are latched 3µ to
8µs after:
1) system power up (internal signal POR going low)
2) trailing edge of PWRDWN# (pin 24) Ground to VCC
3) reset <30.13> is cleared.
Input pins PECLTP (pin 7) and PECLQU (pin 8) are 4 level
input pins with no internal pull-up or pull-down resistors
connected. Nominal values of VCC and 0V are obtained
with directions to VCC or Ground. Nominal values of 2/3
VCC and 1/3 VCC must be developed with external
resistor dividers.
DEFAULT POWER ON CONFIGURATION
This configuration method can be used to set the device
whenever the MII serial management interface is not
available. The logic levels at configuration pins DUPLEX,
SPEED, PECLTP, PECLQU and AD4LIW are decoded and
latched in management control registers 28, 30 and 31
after system power up or after a (low) to (high) transition
at PWRDWN#.
FUNCTIONAL DESCRIPTION
January 2004
MDIO
MDIO
SERIAL MANAGEMENT INTERFACE
The ML6652 has management functions controlled by
three sixteen bit registers and status updated by one
sixteen bit registers. Management Data is input and
output through MDIO and clocked by MDC in an
interface compatible with the protocol defined in clause
22 of IEEE Std 802.3-1998 MII Serial Management
Interface. The address bits PHYAD <4:0> are determined
by voltage levels at configuration pins AD4LIW, AD32,
and AD10.
Management interface read and write timing relationships
are shown in Figures 2 and 3.
MDC
MDC
Final Datasheet
t
SPRS
t
SPWS
Figure 3. Read
Figure 2. Write
t
SPWH
t
SPRH
t
t
CPW
CPW
t
t
CPER
CPER
DS6652-F-02
ML6652
t
t
CPW
CPW