IDT72V201 IDT [Integrated Device Technology], IDT72V201 Datasheet - Page 7

• Manufacturer Part Number: IDT72V201
• Manufacturer: IDT [Integrated Device Technology]

FULL FLAG (FF)
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 256 writes for the IDT72V201, 512 writes for the IDT72V211,
1,024 writes for the IDT72V221, 2,048 writes for the IDT72V231, 4,096 writes
for the IDT72V241 and 8,192 writes for the IDT72V251.
transition of the Write Clock (WCLK).
EMPTY FLAG (EF)
the read pointer is equal to the write pointer, indicating the device is empty.
transition of the Read Clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. If no reads are performed after Reset (RS),
the Programmable Almost-Full flag (PAF) will go LOW after (256-m) writes for
the IDT72V201, (512-m) writes for the IDT72V211, (1,024-m) writes for the
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
(n+1) to (2,048-(m+1))
(2,048-m)
(n+1) to (256-(m+1))
(256-m)
IDT72V231
IDT72V201
1 to n
2,048
1 to n
0
256
(2)
0
(2)
(1)
to 2,047
(1)
to 255
NUMBER OF WORDS IN FIFO
NUMBER OF WORDS IN FIFO
(n+1) to (4,096-(m+1))
(n+1) to (512-(m+1))
(4,096-m)
(512-m)
IDT72V211
IDT72V241
1 to n
1 to n
4,096
512
0
0
(2)
(2)
(1)
to 511
(1)
to 4,095
(n+1) to (1,024-(m+1))
(1,024-m)
(n+1) to (8,192-(m+1))
(8,192-m)
7
IDT72V221
IDT72V221, (2,048-m) writes for the IDT72V231, (4,096-m) writes for the
IDT72V241 and (8,192-m) writes for the IDT72V251. The offset “m” is defined
in the Full Offset registers.
will go LOW at Full-7 words.
the LOW-to-HIGH transition of the Write Clock (WCLK).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
pointer is "n+1" locations less than the write pointer. The offset "n" is defined
in the Empty Offset registers. If no reads are performed after Reset the
Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72V201/72V211/72V221/72V231/72V241/72V251.
(PAE) will go LOW at Empty+7 words.
to the LOW-to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q
IDT72V251
1 to n
1,024
1 to n
8,192
If there is no full offset specified, the Programmable Almost-Full flag (PAF)
The Programmable Almost-Full flag (PAF) is synchronized with respect to
The Programmable Almost-Empty flag (PAE) will go LOW when the read
If there is no empty offset specified, the Programmable Almost-Empty flag
The Programmable Almost-Empty flag (PAE) is synchronized with respect
Data outputs for a 9-bit wide data.
0
(2)
0
(2)
(1)
to 1,023
(1)
to 8,191
0
- Q
8
FF
FF
H
H
H
H
H
H
H
H
L
)
L
COMMERCIAL AND INDUSTRIAL
PAF
PAF
H
H
H
L
L
H
H
H
L
L
TEMPERATURE RANGES
PAE
PAE
H
H
H
H
H
H
L
L
L
L
EF
EF
H
H
H
H
H
H
H
H
L
L