IDT72V201 IDT [Integrated Device Technology], IDT72V201 Datasheet - Page 10

• Manufacturer Part Number: IDT72V201
• Manufacturer: IDT [Integrated Device Technology]

NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
NOTE:
1. When t
(If Applicable)
(If Applicable)
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Q
D
WEN2
WCLK
WEN1
Q
RCLK
D
REN2
REN1,
0
0
WCLK
WEN2
WEN1
RCLK
REN2
t
REN1,
0
- Q
0
SKEW1
SKEW1
- D
OE LOW
- Q
FF
- D
OE
8
EF
8
8
8
t
t
LOW
minimum specification, t
minimum specification, t
ENS
ENS
t
DS
DATA IN OUTPUT REGISTER
t
t
SKEW1
ENS
DATA WRITE 1
NO WRITE
t
SKEW1
t
t
ENH
ENH
DATA IN OUTPUT REGISTER
FRL
FRL
t
ENH
maximum = t
maximum = 2t
t
t
FRL
A
t
WFF
t
CLK
(1)
REF
CLK
+ t
+ t
t
SKEW1
t
ENS
t
ENS
SKEW1
DS
Figure 9. Empty Flag Timing
Figure 8. Full Flag Timing
or t
CLK
+ t
SKEW1
t
WFF
t
10
ENH
t
ENH
t
REF
t
A
DATA READ
t
t
ENS
ENS
t
ENS
NO WRITE
t
DS
DATA WRITE 2
t
ENH
t
A
t
t
t
ENH
SKEW1
ENH
t
SKEW1
DATA READ
t
COMMERCIAL AND INDUSTRIAL
WFF
NEXT DATA READ
t
ENS
t
ENS
TEMPERATURE RANGES
t
FFL
(1)
t
(1)
REF
(1)
NO WRITE
4092 drw11
4092 drw10