S3031BH0 AMCC [Applied Micro Circuits Corporation], S3031BH0 Datasheet - Page 8

• Manufacturer Part Number: S3031BH0
• Description: E4/STM-1/OC-3 ATM TRANSCEIVER
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Figure 10. Criteria for Determination of Transition
Conditions. Compliant to G.775.
In NRZ mode, a logic Low level on the LOSOPT input
will cause the PLL to change its reference to the
reference clock. This pin should be driven by a PECL
compatible level signal detect signal from the fiber
optic receiver.
Serial Clock Output to Data Output Timing
The serial data is clocked out on the falling edge of
RSCLKOP. (See Figure 11.) This timing is valid in
both NRZ and CMI modes.
Serial to Parallel Converter
The Serial to Parallel Converter consists of two 4-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs serial to parallel conversion clocked
by the clock recovery block. The second is the output
holding register. On the falling edge of the free running
POCLK, the data in the serial-in, parallel-out register is
transferred to the output holding register which drives
POUT[3:0].
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance require-
ments are shown in Figure 12.
The S3031B PLL complies with the minimum jitter tol-
erance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 12. The
S3031B PLL also complies with the minimum jitter
tolerance for clock recovery as defined in the ITU-T E4
specification when used as shown in Figure 19.
8
S3031B
Level below Nominal
17
35
“no transition condition” or “transition
nominal value
condition” may be declared
Tolerance range
The signal level 17 is (maximum cable loss +3)
dB below nominal.
The signal level 35 is greater than the maximum
expected cross-talk level.
3 dB
cable loss
maximum
“no transition condition”
“transition condition”
must be declared
must be declared
Figure 11. S3031B Clock to Data Timing
Reference Clock Input
The reference clock input seen in Figure 9 provides
backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to
the same frequency as the Reference Clock
(REFCLK).
Figure 12. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825
Note:
1. Only tested to 20 due to test equipment limitation.
RSCLKOP/N
STM-1 (Electrical) 0.125 19.3
STM-1 (Optical) 0.125 19.3
RSDATOP
Sinusoidal
Input Jitter
Amplitude
OC-3
(UI p-p)
E4
E4/STM-1/OC-3 ATM TRANSCEIVER
TBD
(Hz)
10
f9
A2
A3
A4
TBD
(Hz)
30
f0
f9
(Hz)
300
500
500
200
f1
(kHz)
f0
6.5
6.5
6.5
0.5
f2
August 19, 1999 / Revision D
f1
(kHz)
65
65
65
10
f3
tP SER
f2
(MHz)
1.3
1.3
3.5
—
f4
f3
39
39
A2
15
15
1
1
f4
1.5
1.5 0.15
1.5 0.15
1.5
A3
0.15
0.075
A4