MB15U36PFV FUJITSU [Fujitsu Component Limited.], MB15U36PFV Datasheet - Page 3

• Manufacturer Part Number: MB15U36PFV
• Description: Dual PLL Frequency Synthesizer with On-Chip Prescaler
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

Dual PLL Frequency Synthesizer with On-Chip Prescaler
Pin Descriptions: MB15U36
4
Pin No.
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Fujitsu Microelectronics, Inc.
Pin Name
Vcc
Vp
Do
GND1
fin
Xfin
GND1
OSC
OSC
LD/f
Clock
Data
LE
GND2
Xfin
fin
GND2
Do
Vp
Vcc
1
1
2
2
1
2
1
2
1
2
OUT
IN
OUT
I/O
O
O
O
O
–
–
–
–
–
–
I
I
I
I
I
I
I
I
I
I
Power supply voltage input pin for the RF1-PLL section, the shift register, and the oscillator input buffer. When poweris OFF, latched data
for RF1-PLL is lost.
Power supply for the RF1-PLL charge pump. (Independent of pin 19)
Charge pump output for the RF1-PLL section. Phase detector characteristics can be reversed using the FC-bit.
Ground for the RF1-PLL section.
Prescaler input for the RF1-PLL. Connection to an external VCO should be via AC coupling.
Prescaler complimentary input for the RF1-PLL section. This pin should be grounded via a small capacitor.
Ground for the RF1-PLL section.
External TCXO reference oscillator input or connection to crystal. TCXO should be connected via AC coupling.
Oscillator output or connection to crystal.
Lock detect signal output (LD) or phase comparator monitoring output (f
serial programming data.
Clock input for the 22-bit shift register. One bit of data is shifted into the shift register on a rising edge of the clock.
Serial data input. Data is transferred to the corresponding latch (RF1-ref counter, RF1-prog. counter, RF2-ref. counter, RF2-prog. counter)
according to the control bits settings in the serial programming data.
Load enable signal input. When the LE bit is set to “H”, data in the shift register is transferred to the corresponding latch ac cording to the
control bits settings in the serial programming data.
Ground for the RF2-PLL section.
Prescaler complimentary input for the RF2-PLL section. This pin should be grounded via a small capacitor.
Prescaler input for the RF2-PLL. Connection to an external VCO should be via AC coupling.
Ground for the RF2-PLL section.
Charge pump output for the RF2-PLL section. Phase detector characteristics can be reversed using the FC-bit.
Power supply for the RF2-PLL charge pump. (Independent of pin 2)
Power supply voltage input pin for the RF2-PLL section. When power is OFF, latched data for RF2-PLL is lost.
OSC
LD/f
OSC
GND
GND
Xfin
Vcc
Do
Vp
fin
OUT
OUT
IN
1
1
1
1
1
1
1
(FPT-20P-M03)
1
2
3
4
5
6
7
8
10
9
VIEW
TOP
20
19
18
17
16
15
14
13
12
11
Descriptions
Do
GND
Vcc
Vp
GND
LE
Data
Clock
fin
Xfin
2
2
2
2
2
2
2
out
). The output signal is selected by the LDS and FDS bits in the