MB15U36PFV FUJITSU [Fujitsu Component Limited.], MB15U36PFV Datasheet - Page 16

• Manufacturer Part Number: MB15U36PFV
• Description: Dual PLL Frequency Synthesizer with On-Chip Prescaler
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

Functional Descriptions
Table 8. Binary 7-bit Swallow Counter Data Setting
Note: Divide ratio (A) range = 0 to 127
Table 9. Prescaler Data Setting (SW)
Power-Saving Mode (Intermittent Mode Control)
• The intermittent mode control circuit greatly reduces the PLL power consumption by shuting down various internal functions, as
• The phase detector output, Do, becomes high impedance.
• Serial data can be entered while in the power-saving mode.
• Setting the PS pins “L” releases the power-saving mode, returning the selected PLL to normal operation.
Note: When power (V
Table 10. Power Save Internal Shutdown Logic (PS)
shown in Table 10, depending upon the settings of the power save (PS) bits. Setting the PS bits to “H” enters the corresponding PLL
into the power-saving mode. See the Electrical Characteristics chart for the specific value of current when in the power-saving mode.
Divide Ratio
Prescaler
RF1-PLL
RF2-PLL
PS
Divide
Ratio
(A)
127
H
H
L
L
RF2
0
1
.
CC
A
7
0
0
1
.
) is first applied, the device must be in standby mode, PS = High, for at least 1µs.
PS
SW = “L”
H
H
L
L
RF1
64/65
64/65
A
6
0
0
1
.
A
5
0
0
1
.
RF2-PLL Counters
A
4
0
0
1
.
SW = “H”
128/129
128/129
OFF
OFF
ON
ON
A
3
0
0
1
.
A
2
0
0
1
.
A
1
0
1
1
.
RF1-PLL Counters
OFF
OFF
ON
ON
OSC Input Buffer
Fujitsu Microelectronics, Inc.
MB15U36
OFF
ON
ON
ON
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