lc898093 Sanyo Semiconductor Corporation, lc898093 Datasheet - Page 13

• Manufacturer Part Number: lc898093
• Description: 40 ? Playback/12 ? Write Cd-r/rw Encoder/decoder Ic With Built-in Atapi Interface
• Manufacturer: Sanyo Semiconductor Corporation

5. Spindle Speed Detection Pins
6. Audio Interface Pins
7. RF Amplifier Interface Pins
8. Write Strategy Pins
9. ATIP Decoder Related Pins
<Other Pins>
FG (input)
LOUT, ROUT (output)
LDON (output)
WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT (I/O)
ATIPSYNC (output)
BIDATA, BICLK (I/O)
WOBBLE (input)
ACRCNG (output)
RESET (input)
TEST4 to TEST0 (input)
XTALCK0 (input), XTAL0 (output)
R, VCNT, PDO, R1, VCNT1, PD1, MDC1 (I/O)
SUBSYNC (output)
EFMG (output)
SHOCK (output)
LOCK (output)
DEF (input)
HFL (input)
Input for the speed monitor signal from the spindle driver.
Left and right channel audio signal outputs.
RF amplifier interface.
Write strategy signal connections.
ATIP synchronization detection signal. (For monitoring)
Input mode: Input for the biphase data and biphase clock when an external ATIP demodulator is used.
Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For
monitoring)
Wobble signal input when the internal ATIP demodulator is used.
Outputs the result of the ATIP decoder CRC check. (For monitoring)
The LC898093 reset input. A low level input resets the LC898093.
This pin must be held low for at least 1 µs when power is first applied.
Test inputs. These pins must be connected to ground.
Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder
and decoder blocks, including the DRAM interface.
Consult the manufacturer of the oscillator element concerning the design of the oscillator circuit.
Clock reproduction PLL circuit pins.
Subcode SYNC output signal from the CIRC encoder during encoding. (For monitoring)
Outputs a high-level signal (5 V) during write operations.
Outputs a high level (5 V) when a mechanical shock is detected during decodeing.
Outputs a high level (5 V) when the PLL circuit is locked.
Inputs the defect detection signal.
Inputs the mirror detection signal.
LC898093
No. 6495-13/14