89ttm553 Integrated Device Technology, 89ttm553 Datasheet - Page 6

• Manufacturer Part Number: 89ttm553
• Description: Traffic Manager Co-processing Engine
• Manufacturer: Integrated Device Technology

IDT 89TTM553
FPT_DIN[35:0]
FPT_WR_N
FPT_BW_N[3:0]
FPT_DOUT[35:0]
FPT_VREF[1:0]
GPT_CLK_CP,
GPT_CLK_CN
GPT_CLK_KP,
GPT_CLK_KN
GPT_ADDR[20:0]
GPT_RD_N
GPT_DIN[17:0]
GPT_WR_N
GPT_BW_N[1:0]
GPT_DOUT[17:0]
GPT_VREF
Signal Name
Signal Name
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
I/O Type
I/O Type
Table 4 Flow Parameters Table QDR SRAM (Part 2 of 2)
Table 5 Group Parameters Table QDR SRAM
Dir.
Dir.
—
—
O
O
O
O
O
O
O
O
O
I
I
I
6 of 30
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
—
—
hold times around the rising edges of C and C# during read
operations
asserted, a write cycle is initiated to the external QDR SRAM
devices.
FPT QDR SRAM synchronous write byte enables (active low)
nized to the K and K# during write operations
HSTL reference. Nominally V
GPT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
GPT QDR SRAM address outputs.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations.
GPT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
GPT QDR SRAM synchronous byte enables (active low).
GPT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations.
HSTL reference. Nominally V
FPT QDR SRAM data inputs: Input data must meet setup and
FPT QDR SRAM synchronous write output (active low): When
FPT QDR SRAM write data outputs: Output data is synchro-
GPT QDR SRAM output clock: This clock pair times the con-
GPT QDR SRAM synchronous read output (active low): When
GPT QDR SRAM data inputs: Input data must meet setup and
Remarks
Remarks
DDQ
DDQ
/ 2, so connect to 0.75 V
/ 2, so connect to 0.75 V
March 3, 2005