gvt7164d36 ETC-unknow, gvt7164d36 Datasheet - Page 4

• Manufacturer Part Number: gvt7164d36
• Description: Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (continued)
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE = GND)
March 2, 1998
Rev. 3/98
GALVANTECH
14, 16, 38, 39, 42, 43,50,
66
4, 11, 20, 27, 54, 61, 70,
5, 10, 21, 26, 55, 60, 71,
78, 79, 2, 3, 6-9, 12, 13,
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72-75,
18, 19, 22-25, 28, 29
First Address
First Address
17, 40, 67, 90
15, 41,65, 91
51, 80, 1, 30
QFP PINS
(external)
(external)
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A11
97
86
83
84
85
31
64
77
76
Second Address
Second Address
DQP1, DQP2,
DQP3, DQP4
DQ1-DQ32
SYMBOL
ADSP#
ADSC#
MODE
VCCQ
VSSQ
ADV#
(internal)
(internal)
VCC
CE2
OE#
VSS
NC
ZZ
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground
I/O Supply
Ground
TYPE
Output
Output
Supply
input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Input/
Input
, INC.
-
Third Address
Third Address
(internal)
(internal)
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
Chip enable: This active HIGH input is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data output drivers.
Address Advance: This active LOW input is used to control the internal burst counter. A
HIGH on this pin generates wait cycle (no address advance).
Address Status Processor: This active LOW input, along with CE# being LOW, causes
a new external address to be registered and a READ cycle is initiated using the new
address.
Address Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered. A READ or WRITE cycle is
initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
Snooze: This active HIGH input puts the device in low power consumption standby
mode. For normal operation, this input has to be either LOW or NC (No Connect).
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is
DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet setup and hold times
around the rising edge of CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-
DQ16. DQP3 is parity bit for DQ17-DQ24 and DQP4 is parity bit for DQ25-DQ32.
Core power Supply: +3.3V -5% and +10%
Ground: GND.
Output Buffer Supply: +2.375 to 3.6V
Output Buffer Ground: GND
No Connect: These signals are not internally connected.
64K X 36 SYNCHRONOUS BURST SRAM
4
Fourth Address
Fourth Address
(internal)
(internal)
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A11
DESCRIPTION
Galvantech, Inc. reserves the right to change products or specifications without notice.
PRELIMINARY
GVT7164D36