gvt7164d64 ETC-unknow, gvt7164d64 Datasheet - Page 3

• Manufacturer Part Number: gvt7164d64
• Description: Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS
March 20, 1998
Rev. 3/20/98
GALVANTECH
62, 61, 60, 57, 56,
55, 54, 53, 51, 50,
49, 48, 47, 44, 43,
42
112, 117, 118, 119,
GVT7164D64
107, 108, 111,
PINS
120
114
113
115
121
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
SYMBOL
A0-A15
BWE#
GW#
CLK
CE#
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
TYPE
Input-
Input-
Input-
Input-
Input-
Input-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
128 127 126 125 124 123 122 121 120 119 118 117 116
39
, INC.
40
41
42
Addresses: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK. The burst counter generates
internal addresses associated with A0 and A1, during burst cycle and
wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a
READ cycle. BW1# controls DQ1-DQ8. BW2# controls DQ9-DQ16.
BW3# controls DQ17-DQ24. BW4# controls DQ25-DQ32. BW5#
controls DQ33-DQ40. BW6# controls DQ41-DQ48. BW7# controls
DQ49-DQ56. BW8# controls DQ57-DQ64. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and
must meet the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 64-bit WRITE to occur
independent of the BWE# and BWn# lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write
control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to
gate ADSP#.
PIN ASSIGNMENT (Top View)
43
44
45
46
47
48
49
128-pin QFP
64K X 64 SYNCHRONOUS BURST SRAM
50
51
115 114 113 112 111 110 109
52
3
53
54
55
DESCRIPTION
56
57
58
108 107 106 105 104 103
59
60
61
62
63
Galvantech, Inc. reserves the right to change products or specifications without notice.
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ
GVT7164D64