gvt7164d64 ETC-unknow, gvt7164d64 Datasheet

gvt7164d64

Manufacturer Part Number

gvt7164d64

Description

Synchronous Burst Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT7164D64.pdf (13 pages)

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FEATURES

• Fast access times: 5, 6, and 7ns

• Fast clock speed: 100, 83, and 66 MHz

• Provide high performance 3-1-1-1 access rate

• Fast OE# access times: 5, 6, and 7ns

• Optimal for depth expansion (one cycle chip deselect to

• 3.3V -5% and +10% core power supply, 2.5V or 3.3V I/O

• 5V tolerant inputs except I/O’s

• Clamp diodes to VSS at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Four chip enables for depth expansion and one chip enable

• Address, control, input, and output pipeline registers

• Internally self-timed WRITE CYCLE

• Burst sequence control pins MODE (interleaved or linear

• Automatic power-down for portable applications

• ZZ pin for snooze control

• High density, high speed packages

• High 30pF output drive capability at rated access time

•

OPTIONS

• Timing

• Package

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 3/20/98

GALVANTECH

BURST SRAM

PIPELINED OUTPUT

SYNCHRONOUS

eliminate bus contention)

supply

for address pipeline

burst sequence)

5ns access/10ns cycle

6ns access/12ns cycle

7ns access/15ns cycle

128-pin PQFP

128-pin TQFP

Fax (408) 566-0699

MARKING

-5

-6

-7

, INC.

64K X 64 SYNCHRONOUS BURST SRAM

GENERAL DESCRIPTION

employs high-speed, low power CMOS designs using

advanced

technology. Each memory cell consists of four transistors and

two high valued resistors.

cells with advanced synchronous peripheral circuitry and a 2-

bit counter for internal burst operation. All synchronous

inputs are gated by registers controlled by a positive-edge-

triggered clock input (CLK). The synchronous inputs include

all addresses, all data inputs, address-pipelining chip enable

(CE#), depth-expansion chip enables (CE2#, CE3#, CE2 and

CE3), burst control inputs (ADSC#, ADSP#, and ADV#),

write enables (BW1# to BW8#,and BWE#), and global write

(GW#).

and burst mode control (MODE). The data outputs (Q),

enabled by OE#, are also asynchronous.

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one to eight bytes wide as controlled by the write control

inputs. Individual byte write allows individual byte to be

written. BW1# controls DQ1-DQ8. BW2# controls DQ9-

DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-

DQ32. BW5# controls DQ33-DQ40. BW6# controls DQ41-

DQ48. BW7# controls DQ49-DQ56. BW8# controls DQ57-

DQ64. BW1#, BW2#, BW3#, BW4#, BW5#, BW6#, BW7#,

and BW8# can be active only with BWE# being LOW. GW#

being LOW causes all bytes to be written.

All inputs and outputs are TTL-compatible. The device is

ideally suited for 486, Pentium

systems and for systems that are benefited from a wide

synchronous data bus.

The Galvantech Synchronous Burst SRAM family

The GVT7164D64 SRAM integrates 65,536x64 SRAM

Asynchronous inputs include the output enable (OE#)

Addresses and chip enables are registered with either

Address, data inputs, and write controls are registered on-

The GVT7164D64 operates from a +3.3V power supply.

64K x 64 SRAM

+3.3V SUPPLY,FULLY REGISTERED

INPUTS AND OUTPUTS, BURST COUNTER

triple-layer

polysilicon,

, 680x0, and PowerPC

GVT7164D64

PowerPC is a trademark of IBM Corporation.

Pentium is a trademark of Intel Corporation.

Galvantech, Inc. reserves the right to change

double-layer

products or specifications without notice.

metal

Related parts for gvt7164d64

gvt7164d64 Summary of contents

Page 1

... DQ64. BW1#, BW2#, BW3#, BW4#, BW5#, BW6#, BW7#, and BW8# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. The GVT7164D64 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium systems and for systems that are benefited from a wide synchronous data bus ...

Page 2

... X 64 SYNCHRONOUS BURST SRAM BYTE 1 WRITE D Q BYTE 2 WRITE D Q BYTE 7 WRITE D Q BYTE 8 WRITE D Q ENABLE Input Register Address Register CLR Binary Counter & Logic 2 GVT7164D64 OUTPUT REGISTER DQ1-DQ64 D Q Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 3

... All synchronous inputs must meet setup and hold times around the clock’s rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP#. 3 GVT7164D64 VCCQ 102 DQ32 101 ...

Page 4

... No Connect: These signals are not internally connected. Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A...A10 4 GVT7164D64 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 5

... BWE# BW1# BW2# BW3# BW4 GVT7164D64 WRITE# OE# CLK L-H High L L-H High L L L-H High L L-H High L ...

Page 6

... V OL VCC VCCQ SYM TYP or > Icc 200 IL I 0.4 SB2 SB3 I 50 SB4 ; VCC = MAX; IH CONDITIONS SYMBOL MHz C I VCC = 3. GVT7164D64 MIN MAX UNITS 2.0 VCCQ+0.3 V 2.0 4.6 V -0.3 0 2.4 V 0.4 V 3.1 3.6 V 2.375 VCC UNITS NOTES ...

Page 7

... OEQ OELZ 0 0 OEHZ 2.5 2.5 2 0.5 0.5 0.5 TYP MAX KQ 0.016 CONDITIONS SYMBOL TQFP TYP Still air, soldered on 4. 1.125 inch 4-layer PCB JC 7 GVT7164D64 -7 MAN UNITS NOTES UNITS ...

Page 8

... See Figures 1 and 2 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig / increases with greater t KQHZ is less o C and 20ns cycle time. 8 GVT7164D64 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF Fig. 2 OUTPUT LOAD EQUIVALENT Galvantech, Inc ...

Page 9

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active. March 20, 1998 Rev. 3/20/98 , INC. 64K X 64 SYNCHRONOUS BURST SRAM READ TIMING OEQ t KQLZ OELZ Q(A1) Q(A2) SINGLE READ 9 GVT7164D64 Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) BURST READ Galvantech, Inc. reserves the right to change products or specifications without notice. Q(A2+1) ...

Page 10

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active. March 20, 1998 Rev. 3/20/98 , INC. 64K X 64 SYNCHRONOUS BURST SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 10 GVT7164D64 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Galvantech, Inc. reserves the right to change products or specifications without notice. D(A3+2) ...

Page 11

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2#, CE3#, CE2, and CE3 are active. March 20, 1998 Rev. 3/20/98 , INC. 64K X 64 SYNCHRONOUS BURST SRAM READ/WRITE TIMING Q(A1) Q(A2) D(A3) Q(A3) Pass Through Single Write 11 GVT7164D64 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 12

... Note: All dimensions are in Millimeters. March 20, 1998 Rev. 3/20/98 , INC. 64K X 64 SYNCHRONOUS BURST SRAM PQFP 128 MIN NOM MAX 23.20 23.50 21.90 20.00 20.10 19.90 17.20 17.50 15.90 14.00 14.10 13.90 2.80 3.10 3.40 2.55 2.80 3.05 0.73 0.88 1.03 0.17 0.20 0.27 0.50 Basic 12 GVT7164D64 L b TQFP 128 MIN NOM MAX 22.00 22.10 20.00 20.10 16.00 16.10 14.00 14.10 1.40 1.50 1.60 1.35 1.40 1.45 0.45 0.60 0.75 0.17 0.20 0.27 0.50 Basic Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 13

... Galvantech Prefix Part Number March 20, 1998 Rev. 3/20/98 , INC. 64K X 64 SYNCHRONOUS BURST SRAM 13 GVT7164D64 Speed (5 =5ns access/10ns cycle 6 = 6ns access/12ns cycle 7 = 7ns access/15ns cycle) , Package (Q = 128 PIN PQFP T = 128 PIN TQFP) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

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