gvt71256d18 ETC-unknow, gvt71256d18 Datasheet - Page 4

• Manufacturer Part Number: gvt71256d18
• Description: 256k Synchronous Burst Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (continued)
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE = GND)
November 6, 1998
Rev. 11/98
GALVANTECH
1B, 7B, 1C, 7C, 2D, 4D,
7D, 1E, 6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R, 7R, 1T,
4T, 2U, 3U, 4U, 5U, 6U
6L, 6N, 1D, 2E, 2G, 1H,
5G, 3H, 5H, 3K, 5K, 3L,
6D, 7E, 6F, 7G, 6H, 7K,
3M, 5M, 3N, 5N, 3P, 5P
3D, 5D, 3E, 5E, 3F, 5F,
1A, 7A, 1F, 7F, 1J, 7J,
4C, 2J, 4J, 6J, 4R
First Address
First Address
1M, 7M, 1U, 7U
2K, 1L, 2M, 1N
BGA PINS
(external)
(external)
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A11
2P, 7P
4G
3R
2B
4F
4A
4B
7T
69, 72, 73, 8, 9, 12,
1-3, 6, 7, 14, 16,
25, 28-30, 38, 39,
42, 43, 51-53, 56,
57, 66, 75, 78, 79,
80, 95, 96
58, 59, 62, 63, 68,
13, 18, 19, 22, 23
5, 10, 21, 26, 55,
Second Address
Second Address
4, 11, 20, 27, 54,
17, 40, 67, 90
TQFP PINS
15, 41,65, 91
61, 70, 77
60, 71, 76
(internal)
(internal)
74, 24
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
97
86
83
84
85
31
64
DQ1-DQ16
SYMBOL
, INC.
ADSC#
ADSP#
DQP1,
MODE
VCCQ
DQP2
VSSQ
ADV#
VCC
CE2
OE#
VSS
NC
ZZ
Third Address
Third Address
(internal)
(internal)
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground Output Buffer Ground: GND
I/O Supply Output Buffer Supply: +2.5V or 3.3V
Asynchro-
Ground
Supply
TYPE
Output
Output
input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Input/
Input
nous
-
256K X 18 SYNCHRONOUS BURST SRAM
Chip enable: This active HIGH input is used to enable the device.
Output Enable: This active LOW asynchronous input enables the data
output drivers.
Address Advance: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address
advance).
Address Status Processor: This active LOW input, along with CE# being
LOW, causes a new external address to be registered and a READ cycle
is initiated using the new address.
Address Status Controller: This active LOW input causes device to be
de-selected or selected along with new external address to be registered.
A READ or WRITE cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects
LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED
BURST.
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC (No Connect).
Data Inputs/Outputs: Low Byte is DQ1-DQ8. High Byte is DQ9-DQ16.
Input data must meet setup and hold times around the rising edge of
CLK.
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is
parity bit for DQ9-DQ16.
Power Supply: +3.3V -5% and +10%
Ground: GND.
No Connect: These signals are not internally connected.
4
Fourth Address
Fourth Address
(internal)
(internal)
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A11
Galvantech, Inc. reserves the right to change products or specifications without notice.
DESCRIPTION
GVT71256D18