gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 14

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

Note:
1. Q(A
2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2#
3. When either one of the Chip enables (CE#, CE2 or CE2#) is sampled inactive at the rising clock edge, a chip
4
July 23, 1998
Rev. 7/98
. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated
GALVANTECH
DATA Out (Q)
BWa#, BWb#
DATA In (D)
corresponding to address A
is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on
this waveform, CE2 is HIGH.
deselect cycle is initiated. The data-bus High-Z one cycle after the initiation of the deselect cycle. This allows for
any pending data transfers (reads or writes) to be completed.
when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
(See Note)
ADDRESS
ADV/LD#
1
) represents the first output from the external address A
CKE#
R/W#
CLK
OE#
CE#
A
1
t
t
t
S
S
S
t
Q(A
OELZ
t
KQLZ
t
OEQ
t
KQ
1
A
)
3
2
, etc.
t
S
t
t
t
H
H
H
Q(A
, INC.
2
)
t
KQHZ
t
t
t
S
S
KC
t
t
KQX
H
CE# TIMING
t
KL
A
256K X 18 FLOW-THROUGH ZBL SRAM
3
14
t
t
H
H
t
D(A
SD
1
. D(A
t
HD
3
)
t
KH
3
) represents the input data to the SRAM
A
Galvantech, Inc. reserves the right to change products or specifications without notice.
4
Q(A
4
)
GVT71256ZB18
t
OEHZ
A
5