gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet

gvt71256zb18

Manufacturer Part Number

gvt71256zb18

Description

256k Flow-through Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT71256ZB18.pdf (16 pages)

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Company:

Meier Automation Equipment Co., Limited

Part Number:

gvt71256zb18T-10

Manufacturer:

GALVANTE

Quantity:

20 000

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FEATURES

• Zero Bus Latency, no dead cycles between write and read

• Fast clock speed: 100, 83, 67, and 50MHz

• Fast access time: 9, 10, 11, 15ns

• Internally synchronized registered outputs eliminate the

• Single 3.3V -5% and +5% power supply

• Single R/W# (READ/WRITE) control pin

• Positive clock-edge triggered, address, data, and control

• Interleaved or linear 4-word burst capability

• Individual byte write (BWa# - BWb#) control (may be tied

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• SNOOZE MODE for low power standby

• Automatic power down

• Packaged in a JEDEC standard 100-pin TQFP package

OPTIONS

• Timing

• Packages

GENERAL DESCRIPTION

dead cycles when transitions from READ to WRITE or vice

versa. This SRAM is optimized for 100 percent bus utilization

and achieves Zero Bus Latency (ZBL). It integrates

262,144x18 SRAM cells with advanced synchronous

peripheral circuitry and a 2-bit counter for internal burst

operation. The Galvantech Synchronous Burst SRAM family

employs high-speed, low power CMOS designs using

advanced

technology. Each memory cell consists of four transistors and

two high valued resistors.

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 7/98

GALVANTECH

ZBL SRAM

FLOW-THRU OUTPUT

SYNCHRONOUS

cycles

need to control OE#

signal registers

LOW)

9.0ns access/10.0ns cycle

10.0ns access/12.0ns cycle

11.0ns access/15.0ns cycle

15.0ns access/20.0 cycle

100-pin TQFP

The GVT71256ZB18 SRAM is designed to eliminate

triple-layer

Fax (408) 566-0699 Web Site www.galvantech.com

polysilicon,

MARKING

-9

-10

-11

-15

double-layer

, INC.

metal

256K X 18 FLOW-THROUGH ZBL SRAM

by a positive-edge-triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

depth-expansion chip enables (CE#, CE2# and CE2), cycle

start input (ADV/LD#), clock enable (CKE#), byte write

enables (BWa# and BWb#), and read-write control (R/W#).

during one clock cycle, and one cycle later, its associated data

occurs, either read or write.

GVT71256ZB18 to be suspended as long as necessary. All

synchronous inputs are ignored when (CKE#) is high and the

internal device registers will hold their previous values.

allow the user to deselect the device when desired. If any one

of these three are not active when ADV/LD# is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state one cycle after chip is deselected or a write

cycle is initiated.

In the burst mode, the GVT71256ZB18 provides four cycles

of data for a single address presented to the SRAM. The order

of the burst sequence is defined by the MODE input pin. The

MODE pin selects between linear and interleaved burst

sequence. The ADV/LD# signal is used to load a new external

address (ADV/LD#=LOW) or increment the internal burst

counter (ADV/LD#=HIGH)

sequence select (MODE) are the asynchronous signals. OE#

can be used to disable the outputs at any given time. ZZ may

be tied to LOW if it is not used.

volume 3.3V CMOS process, and is packaged in a JEDEC

Standard 14mm x 20mm 100-pin thin plastic quad flatpack

(TQFP) for high board density.

All synchronous inputs are gated by registers controlled

Address and control signals are applied to the SRAM

A clock enable (CKE#) pin allows operation of the

There are three chip enable pins (CE#, CE2, CE2#) that

The GVT71256ZB18 has an on-chip 2-bit burst counter.

Output enable (OE#), snooze enable (ZZ) and burst

The GVT71256ZB18 utilizes high performance high

256K x 18 SRAM

+3.3V SUPPLY, 2-BIT BURST COUNTER

SELECTABLE BURST MODE

GVT71256ZB18

Galvantech, Inc. reserves the right to change

products or specifications without notice.

Related parts for gvt71256zb18

gvt71256zb18 Summary of contents

Page 1

... A clock enable (CKE#) pin allows operation of the GVT71256ZB18 to be suspended as long as necessary. All synchronous inputs are ignored when (CKE#) is high and the internal device registers will hold their previous values. ...

Page 2

... The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. July 23, 1998 Rev. 7/98 , INC. 256K X 18 FLOW-THROUGH ZBL SRAM Input Registers 2 GVT71256ZB18 Address Control Control Logic Sel Mux Output Buffers DQa-DQb, DQPa, DQPb ...

Page 3

... ADV/LD Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. Input- Clock: This is the clock input to GVT71256ZB18. Except for OE#, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. 3 ...

Page 4

... TYPE Input- Synchronous Active Low Chip Enable: CE# and CE2# are used with CE2 to enable the GVT71256ZB18. CE# or CE2# sampled HIGH or CE2 sampled LOW, along with ADV/ Synchronous LD# LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be HIGH-Z one clock cycle after chip deselect is initiated. ...

Page 5

... BWa# BWb n+21 n+22 n+ GVT71256ZB18 n+24 n+25 n+26 n+ Galvantech, Inc. reserves the right to change products or specifications without notice ...

Page 6

... High-Z means HIGH IMPEDANCE. 6 GVT71256ZB18 DQ CKE# BWx# OE# (1 cycle later High High High High ...

Page 7

... TYP or > Icc 150 IL 2 MAX I 5 SB2 SB3 I 40 SB4 ; VCC = MAX /2. increases with greater output loading and faster cycle times and 20ns cycle time. 7 GVT71256ZB18 MIN MAX UNITS NOTES 2.0 VCC+0.3 V 2.0 4.6 V -0.5 0 2 ...

Page 8

... CONDITIONS SYMBOL MHz C I VCC = 3. CONDITIONS SYMBOL TQFP TYP Still air, soldered on 4. 1.125 inch 4-layer PCB KQHZ is less than KQLZ and 8 GVT71256ZB18 - 67MHz 50MHz MIN MAX MIN MAX UNITS 15.0 20.0 ns 4.0 4.0 ns 4.0 4.0 ns 11.0 15.0 ns 3.0 3.0 ns 4.0 4.0 ns 5.0 5.0 ns 5.0 5 ...

Page 9

... Output load July 23, 1998 Rev. 7/98 , INC. 256K X 18 FLOW-THROUGH ZBL SRAM OUTPUT LOADS 1.0V/ns 1.5V 1.5V See Figures 1 and 2 Fig. 2 OUTPUT LOAD EQUIVALENT 9 GVT71256ZB18 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 351 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 10

... H t KQX Q(A ) Q(A +1) Q(A + Read BURST READ . Q GVT71256ZB18 t (Burst Wraps around (CKE# HIGH , eliminates KQHZ to initial state) current L-H clock edge) Q(A +3) Q Deselect ) represents the first output from the external 2 , etc. where 2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 11

... D(A ) D(A +1) D(A + Write Burst Write ) represents the first input to the external address 2 11 GVT71256ZB18 BW (CKE# HIGH, eliminates (Burst Wraps around current L-H clock edge) to initial state) D(A +3) D Deselect , etc. where address bits 2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 12

... BW KQLZ KQX Q Read D Write Write . D GVT71256ZB18 Q Read D(A D Write ) represents the input data to the SRAM 2 Galvantech, Inc. reserves the right to change products or specifications without notice D ...

Page 13

... KQHZ ) KQX D D GVT71256ZB18 represents the input data to the SRAM Galvantech, Inc. reserves the right to change products or specifications without notice Q ...

Page 14

... CE# TIMING KQHZ Q KQX D D GVT71256ZB18 OEHZ Q represents the input data to the SRAM Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 15

... GALVANTECH 100 Pin TQFP Package Dimensions # 1 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters July 23, 1998 Rev. 7/98 , INC. 256K X 18 FLOW-THROUGH ZBL SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 15 GVT71256ZB18 0.30 + 0.08 0.60 + 0.15 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 16

... Galvantech Prefix Part Number July 23, 1998 Rev. 7/98 , INC. 256K X 18 FLOW-THROUGH ZBL SRAM 16 GVT71256ZB18 Speed (9 = 9.0ns access/10ns cycle 10 = 10.0ns access/12ns cycle 11 = 11.0ns access/15ns cycle 15 = 15.0ns access/20ns cycle) Package (T = 100 PIN TQFP) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

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